MC81F4x16
25.4 Procedure
Initialization
Following steps initialize the IIC slave.
1. Set SCL and SDA pins as an alternative mode.
Set the R1CONH[7~4] bits by “1010b”.
2. Set the slave address by setting the IICAR register.
3. Enable IIC module and the interrupt :
Set the ACKE bit by „1‟
Set the IICEN bit by „1‟
Set the IICIFEN bit by „1‟. ( If it is cleared by „0‟, IIC interrupt is not occurred )
-> Or you can simply set the IICSCR register by „E0h‟.
After finish above steps, IIC interrupt is enabled. So The IIC interrupt will be generated after receive
or transmit one byte.
Interrupt Routine Procedure
Simply say, when you write a byte to the IICSCR, it is transmitted and when a byte is received, you
can read it from the IICDSR register.
But, the master has a right to decide the read/write mode. And the master sends 1-bit R/W mode flag
after 7-bit slave address. And it is stored in the IICTR(IICSCR.3) bit when it is received.
So you can recognize current Rx/Tx mode. And you have to react based on the IICTR(IICSCR.3) bit.
The IICTR(IICSCR.3) bit equals „1‟ means that the master want to read from the slave. So, In this
case, Slave-IIC‟s mode is changed into „transmit mode‟ automatically. So, in this case you have to
write a data to the IICDSR register as you want.
The IICTR(IICSCR.3) bit equals „0‟ means that the master want to write to the slave. So, In this case,
Slave-IIC‟s mode is changed into „receive mode‟ automatically. So, in this case you have to read a
data from the IICDSR register.
Before finish the IIC interrupt routine, you have to clear the IICIF bit. When the IICIF bit is cleared, the
SCL line is released. If it is not cleared, the SCL line is holding down to low status. While in this
condition, master can‟t continue the IIC communication.
In order to recognize current received byte‟s position in the message, you have to count the IIC
interrupts. Based on the position information
October 19, 2009 Ver.1.35
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