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FTLF1424P2WCD 参数 Datasheet PDF下载

FTLF1424P2WCD图片预览
型号: FTLF1424P2WCD
PDF下载: 下载PDF文件 查看货源
内容描述: 4个千兆符合RoHS长波长SFP收发器 [4 Gigabit RoHS Compliant Long-Wavelength SFP Transceiver]
分类和应用: 光纤通信
文件页数/大小: 11 页 / 482 K
品牌: FINISAR [ FINISAR CORPORATION. ]
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FTLF1424P2xCR and FTLF1424P2xCD SFP Product Specification – August 2006
Finisar
I.
Pin
1
2
3
4
5
6
7
Pin Descriptions
Symbol
V
EET
T
FAULT
T
DIS
MOD_DEF(2)
MOD_DEF(1)
MOD_DEF(0)
Rate Select
Name/Description
Transmitter Ground (Common with Receiver Ground)
Transmitter Fault. Not supported.
Transmitter Disable. Laser output disabled on high or open.
Module Definition 2. Data line for Serial ID.
Module Definition 1. Clock line for Serial ID.
Module Definition 0. Grounded within the module.
Open or Low =
1.063 Gb/s or 2.125 Gb/s Fibre Channel, 1.25 Gb/s
Gigabit Ethernet (Low Bandwidth)
High =
2.125 or 4.25 Gb/s Fibre Channel (High Bandwidth)
Loss of Signal indication. Logic 0 indicates normal operation.
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted DATA in. AC Coupled.
Transmitter Inverted DATA in. AC Coupled.
Transmitter Ground (Common with Receiver Ground)
Ref.
1
2
3
3
3
4
8
9
10
11
12
13
14
15
16
17
18
19
20
LOS
V
EER
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
5
1
1
1
1
1
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on T
DIS
>2.0V or open, enabled on T
DIS
<0.8V.
3. Should be pulled up with 4.7k - 10 kohms on host board to a voltage between 2.0V and 3.6V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4.
For Rate Selectable version only:
In accordance with SFF Committee SFF-8079 Draft, Rev.1.6,
Table 3. Note that rate select can also be set through 2-wire bus in accordance with SFF-8472
6
at Bit
3, Byte 110, Address A2h (note: writing ‘1’ selects full bandwidth operation). Rate select is the logic
OR of the input state of Rate Select Pin and 2-wire bus. Non Rate Selectable version can operate at 1x,
2x, 4x Fibre Channel independent of rate select pin setting.
5. LOS is open collector output. Should be pulled up with 4.7k – 10 kohms on host board to a voltage
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
1
2
3
4
VeeT
TD-
TXFault
TD+
TX Disable
VeeT
MOD-DEF(2)
VccT
16
15
14
13
12
11
MOD-DEF(1)
VccR
6
7
8
9
10
MOD-DEF(0)
VeeR
Rate Select
RD+
LOS
RD-
VeeR
VeeR
VeeR
17
18
19
20
Towards
Bezel
5
Towards
ASIC
Pinout of Connector Block on Host Board
©
Finisar Corporation August 31, 2006 Rev D
Page 2