FTLF8524E2xNy 2x7 Pin SFF Product Specification – July 2005
I.
Pin
MS
1
2
3
4
5
6
7
8
9
10
A
B
C
D
Notes:
Pin Descriptions
Symbol
MS
V
EER
V
CCR
SD
RD-
RD+
V
CCT
V
EET
T
DIS
TD+
TD-
SDA
SCL
Rate
Select
Reserved
Name/Description
Mounting Studs are for mechanical attachment and are connected to
chassis ground.
Chassis ground is internally isolated from circuit
grounds.
Connection to user’s ground plane is recommended.
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
Signal Detect. Logic 1 indicates normal operation.
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Disable
Transmitter Non-Inverted DATA in. AC Coupled.
Transmitter Inverted DATA in. AC Coupled
Two Wire Digital Diagnostics Data Interface
Two Wire Digital Diagnostics Clock Interface
1.063 Gb/s or 2.125 Gb/s Fibre Channel,
Open or Low =
(Low Bandwidth)
2.125 or 4.25 Gb/s Fibre Channel (High Bandwidth)
High =
Logic Family
NA
NA
NA
LVTTL
See Rx spec.
See Rx spec.
NA
NA
LVTTL
See Tx spec.
See Tx spec.
See Note 1
See Note 1
LVTTL
See Note 2
NA
1.
Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and V
CC
.
2.
For Rate Selectable version only:
In accordance with SFF Committee SFF-8079 Draft Rev. 1.6,
Table 3. Note that rate select can also be set through 2-wire bus in accordance with SFF-8472
5
at Bit
3, Byte 110, Address A2h (note: writing ‘1’ selects full bandwidth operation). Rate select is the logic
OR of the input state of Rate Select Pin and 2-wire bus. Non Rate Selectable version can operate at 1x,
2x, 4x Fibre Channel independent of rate select pin setting.
MS
D B 10 …
6
TOP VIEW
CA1
…
5
MS
Finisar Corporation July 12, 2005 RevG
Page 2
FINISAR [ FINISAR CORPORATION. ]
