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FTLX1472M3BCL 参数 Datasheet PDF下载

FTLX1472M3BCL图片预览
型号: FTLX1472M3BCL
PDF下载: 下载PDF文件 查看货源
内容描述: 10Gb / s的, 2 / 10公里单模,多速率SFP收发器 [10Gb/s, 2/10km Single Mode, Multi-Rate SFP Transceiver]
分类和应用:
文件页数/大小: 11 页 / 648 K
品牌: FINISAR [ FINISAR CORPORATION. ]
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FTLX1472M3BCL Multi-rate 10G SFP+ Product Specifications
I.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Descriptions
Symbol
V
EET
T
FAULT
T
DIS
SDA
SCL
MOD_ABS
RS0
RX_LOS
RS1
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
Name/Description
Transmitter Ground
Transmitter Fault
Transmitter Disable. Laser output disabled on high or open.
2-wire Serial Interface Data Line
2-wire Serial Interface Clock Line
Module Absent. Grounded within the module
Rate Select 0.
Loss of Signal indication. Logic 0 indicates normal operation.
Rate Select 1.
Receiver Ground
Receiver Ground
Receiver Inverted DATA out. AC Coupled.
Receiver Non-inverted DATA out. AC Coupled.
Receiver Ground
Receiver Power Supply
Transmitter Power Supply
Transmitter Ground
Transmitter Non-Inverted DATA in. AC Coupled.
Transmitter Inverted DATA in. AC Coupled.
Transmitter Ground
Ref.
1
2
3
2
2
2
4
5
4
1
1
1
1
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. T
is an open collector/drain output, which should be pulled up with a 4.7k – 10k Ohms resistor on
FAULT
3.
4.
5.
the host board if intended for use. Pull up voltage should be between 2.0V to Vcc + 0.3V. A high
output indicates a transmitter fault caused by either the TX bias current or the TX output power
exceeding the preset alarm thresholds. A low output indicates normal operation. In the low state, the
output is pulled to <0.8V.
Laser output disabled on T
DIS
>2.0V or open, enabled on T
DIS
<0.8V.
Internally pulled down per SFF-8431 Rev 2.0. See Sec. X for the logic table to use for the internal
CDRs locking modes.
LOS is open collector output. Should be pulled up with 4.7k – 10kΩ on host board to a voltage
between 2.0V and 3.6V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
1
VeeT
TD-
2
TX_Fault
TD+
3
TX_Disable
VeeT
4
SDA
VccT
20
19
18
17
16
Towards
Bezel
5
SCL
VccR
15
6
MOD_ABS
VeeR
14
Towards
ASIC
7
RS0
RD+
13
8
RX_LOS
RD-
12
9
RS1
VeeR
11
VeeR
10
Figure 1. Diagram of Host Board Connector Block Pin Numbers and Names.
©
Finisar Corporation - February 2012
Rev. B
Page 2