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FWLF1621P2T61 参数 Datasheet PDF下载

FWLF1621P2T61图片预览
型号: FWLF1621P2T61
PDF下载: 下载PDF文件 查看货源
内容描述: 多速率CWDM SFP可插拔收发器 [Multi-rate CWDM Pluggable SFP Transceiver]
分类和应用:
文件页数/大小: 12 页 / 506 K
品牌: FINISAR [ FINISAR CORPORATION. ]
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FWLF1621P2Txx SFP Product Specification – November 2007
Finisar
I.
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Descriptions
Symbol
V
EET
T
FAULT
T
DIS
MOD_DEF(2)
MOD_DEF(1)
MOD_DEF(0)
Rate Select
LOS
V
EER
V
EER
V
EER
RD-
RD+
V
EER
V
CCR
V
CCT
V
EET
TD+
TD-
V
EET
Name/Description
Transmitter Ground (Common with Receiver Ground)
Transmitter Fault. Not supported.
Transmitter Disable. Laser output disabled on high or open.
Module Definition 2. Data line for Serial ID.
Module Definition 1. Clock line for Serial ID.
Module Definition 0. Grounded within the module.
No connection required
Loss of Signal indication. Logic 0 indicates normal operation.
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Ground (Common with Transmitter Ground)
Receiver Inverted DATA out. AC Coupled
Receiver Non-inverted DATA out. AC Coupled
Receiver Ground (Common with Transmitter Ground)
Receiver Power Supply
Transmitter Power Supply
Transmitter Ground (Common with Receiver Ground)
Transmitter Non-Inverted DATA in. 100 ohm termination between TD+
and TD-, AC Coupled thereafter.
Transmitter Inverted DATA in. See TD+
Transmitter Ground (Common with Receiver Ground)
Ref.
1
2
3
3
3
4
5
1
1
1
1
1
1
Notes:
1. Circuit ground is internally isolated from chassis ground.
2. Laser output disabled on T
DIS
>2.0V or open, enabled on T
DIS
<0.8V.
3. Should be pulled up with 4.7k – 10kohms on host board to a voltage between 2.0V and 5.5V.
MOD_DEF(0) pulls line low to indicate module is plugged in.
4. Finisar 2x receiver achieves simultaneous 1x and 2x operation without active control.
5. LOS is open collector output. Should be pulled up with 4.7k – 10kohms on host board to a voltage
between 2.0V and 5.5V. Logic 0 indicates normal operation; logic 1 indicates loss of signal.
VeeT
1
2
3
4
VeeT
TD-
TXFault
TD+
TX Disable
VeeT
MOD-DEF(2)
VccT
20
19
18
17
16
15
14
13
12
11
Towards
Bezel
5
6
7
8
9
10
MOD-DEF(1)
VccR
MOD-DEF(0)
VeeR
Rate Select
RD+
LOS
RD-
VeeR
VeeR
VeeR
Towards
ASIC
Diagram of Host Board Connector Block Pin Numbers and Names
©
Finisar Corporation November 2007 Rev.A Preliminary and Confidential
Page 2