F71612
P
- Power.
Pin No
1
Pin Name
D+
Type
I/O
12t_1.5k
PWR
Description
VDD D+. Different data bus conforming to USB standard. Internal pull
high 1.5kΩ.
2
3
D-
PSOUT#
I/O
12t
OD
12_5v
VDD D-. Different data bus conforming to USB standard.
VDD Panel Switch Output. This pin is low active and pulse output. It is
power on request output.
4
STATE_SEL IN
ts
VDD This pin is for wake up function.
For Portable Product
Pull this pin to high for USB wake up.
Pull this pin to high and suggest
For MB System Product
connecting with one of S4/S5/PWROK/GPIO pin.
MB System in S4/S5 state: Wake up signal will be asserted by
PSOUT# pin in S4/S5 state.
MB System in S3 state: Wake up signal will be asserted by USB
interface in S3 state.
5
6
7
XTALIN/48M IN
t
XTALOUT
PWCTL
O
12
OD
12
VDD 12MHz/48MHz clock input.
VDD 12MHz/48MHz clock output.
VDD RX_LR learning power control pin. Suggest external pull high to
3.3V and the clock input source will be selected to 12MHz input.
8
9
10
11
GND
SCL
SDA
TX1
P
OD
12_5V
OD
12_5V
O
12
VDD Ground pin.
VDD I2C interface serial clock
VDD I2C interface serial data
VDD IR transmits port 1.
Pull down 100k resister to ground
No resister connects to ground
12
TX0
O
12
VDD IR transmits port 0.
TX/RX functions selection.
RX function only.
Pull down 100k resister to ground ( TX/RX functions
selection.
No resister connects to ground ( RX function only.
(P.S One of TX pins pull down 100K resister to ground, chip
feature will be selected to TX and RX functions, if not, chip
will be selected to RX function only.)
13
14
15
LED#
RX_LR#
RX_NR#
OD16_5V
IN
ts_5v
IN
ts_5v
VDD LED output pin.
VDD IR receiver port1 ( wide band for learning)
VDD IR receiver port0 (long range)
-3-
Dec.,
2007
V0.22P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
