F75386
(a) SMBus write to internal address register followed by the data byte
0
SCL
SDA
Start By
Master
7
8
0
7
8
1
0
0
1
1
0
0
R/W
Ack
by
386
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
386
Frame 1
Serial Bus Address Byte
0
Frame 2
Internal Index Register Byte
7
SCL (Continued)
SDA (Continued)
D7
D6
D5
D4
D3
D2
D1
D0
8
Stop
by
Master
Frame 3
Data Byte
Figure 1. Serial Bus Write to Internal Address Register followed by the Data Byte
(b) Serial bus write to internal address register only
0
SCL
SDA
Start By
Master
7
8
0
7
8
1
0
0
1
1
0
0
R/W
Ack
by
386
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
386
Stop by
Master
Frame 1
Serial Bus Address Byte
0
Frame 2
Internal Index Register Byte
Figure 2. Serial Bus Write to Internal Address Register Only
(c) Serial bus read from a register with the internal address register prefer to desired location
0
SCL
SDA
Start By
Master
7
8
0
7
8
1
0
0
1
1
0
0
R/W
Ack
by
386
D7
D6
D5
D4
D3
D2
D1
D0
Ack
by
Master
Stop by
Master
Frame 1
Serial Bus Address Byte
0
Frame 2
Internal Index Register Byte
Figure 3. Serial Bus Read from Internal Address Register
(d) Alert Response Address
0
SCL
SDA
Start By
Master
7
8
0
7
8
0
0
0
1
1
0
0
R/W
Ack
by
386
0
1
0
0
1
1
0
0
Ack
by
Master
Stop by
Master
Frame 1
Alert Response Address
0
Frame 2
Device Address
Figure 4. Alert Response Address
F75386
-4-
July,
2007
V0.27P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
