F81865
F9
E0
E1
E2
E3
EF
D0
D1
D2
D3
C0
C1
C2
C3
B0
B1
B2
B3
A0
A1
A2
A3
90
91
92
93
GPIO0 Interrupt Status Register
GPIO1 Output Enable Register
GPIO1 Output Data Register
GPIO1 Pin Status Register
GPIO1 Drive Enable Register
LED Mode Register
GPIO2 Output Enable Register
GPIO2 Output Data Register
GPIO2 Pin Status Register
GPIO2 Drive Enable Register
GPIO3 Output Enable Register
GPIO3 Output Data Register
GPIO3 Pin Status Register
GPIO3 Drive Enable Register
GPIO4 Output Enable Register
GPIO4 Output Data Register
GPIO4 Pin Status Register
GPIO4 Drive Enable Register
GPIO5 Output Enable Register
GPIO5 Output Data Register
GPIO5 Pin Status Register
GPIO5 Drive Enable Register
GPIO6 Output Enable Register
GPIO6 Output Data Register
GPIO6 Pin Status Register
GPIO6 Drive Enable Register
0
0
1
-
0
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
-
-
-
-
0
0
1
-
0
-
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
-
-
-
-
0
0
1
-
0
-
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
-
-
-
-
0
0
1
-
0
-
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
0
1
-
0
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
0
1
-
0
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
0
1
-
0
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
0
1
-
0
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
0
1
-
0
WDT Device Configuration Registers (LDN CR07)
Register
0x[HEX]
30
60
61
F5
F6
FA
Register Name
WDT Device Enable Register
Base Address High Register
Base Address Low Register
WDT Control Register
WDT Timer Register
WDT PME Enable Register
Default Value
MSB
-
0
0
0
0
0
-
0
0
0
0
0
-
0
0
0
0
-
-
0
0
0
0
-
-
0
0
0
0
-
-
0
0
0
0
-
LSB
-
0
0
0
0
-
0
0
0
0
0
0
SPI Device Configuration Registers (LDN CR08)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
72
May, 2010
V0.28P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
