Feature Integration Technology Inc.
Fintek
8.18 Master Setting Register – Index 1Ch.......................................................................... 23
8.19 Master Setting Register – Index 1Dh.......................................................................... 24
8.20 Refresh Address Register (Low Byte) – Index 1Eh..................................................... 24
8.21 Refresh Address Register (High Byte) – Index 1Fh .................................................... 24
8.22 Address1 Decode Mask Register – Index 20h............................................................ 24
8.23 Address1 Decode Register (Low Byte) – Index 21h ................................................... 24
8.24 Address1 Decode Register (High Byte) – Index 22h .................................................. 25
8.25 Address2 Decode Mask Register – Index 23h............................................................ 25
8.26 Address2 Decode Register (Low Byte) – Index 24h ................................................... 25
8.27 Address2 Decode Register (High Byte) – Index 25h .................................................. 25
8.28 ROM1 Decoder Mask Low Byte Register – Index 0x28.............................................. 26
8.29 ROM Decoder Mask (High Byte) Register – Index 0x29............................................. 26
8.30 ROM Decoder Address (Low Byte) Register – Index 0x2A......................................... 26
8.31 ROM Decoder Address (High Byte) Register – Index 0x2B........................................ 26
8.32 ROM2 Decoder Mask Low Byte Register – Index 0x2C ............................................. 27
8.33 ROM2 Decoder Mask (High Byte) Register – Index 0x2D.......................................... 27
8.34 ROM2 Decoder Address (Low Byte) Register – Index 0x2E....................................... 27
8.35 ROM2 Decoder Address (High Byte) Register – Index 0x2F ...................................... 27
8.36 ADDR3 Decoder Mask High Byte Register – Index 0x30 ........................................... 28
8.37 ADDR3 Decoder Address Low Byte Register – Index 0x31........................................ 28
8.38 ADDR3 Decoder Address High Byte Register – Index 0x32....................................... 28
8.39 ADDR4 Decoder Mask High Byte Register – Index 0x33 ........................................... 28
8.40 ADDR4 Decoder Address Low Byte Register – Index 0x34........................................ 29
8.41 ADDR4 Decoder Address High Byte Register – Index 0x35....................................... 29
8.42 KBC Decoder Mask Register – Index 0x36 ................................................................ 29
8.43 KBC Decoder Address Low Byte Register – Index 0x37 ............................................ 30
8.44 KBC Decoder Address High Byte Register – Index 0x38............................................ 30
8.45 MC Decoder Mask Register – Index 0x39 .................................................................. 30
8.46 MC Decoder Address Low Byte Register – Index 0x3A.............................................. 30
8.47 MC Decoder Address High Byte Register – Index 0x3B............................................. 31
8.48 RTC Decoder Mask Register – Index 0x3C................................................................ 31
8.49 RTC Decoder Address Low Byte Register – Index 0x3D............................................ 31
8.50 RTC Decoder Address High Byte Register – Index 0x3E ........................................... 31
8.51 IOH Decoder Mask Register – Index 0x3F ................................................................. 32
8.52 IOH Decoder Address Low Byte Register – Index 0x40 ............................................. 32
8.53 IOH Decoder Address High Byte Register – Index 0x41............................................. 32
8.54 Edge Detector Status Register – Index 0x50 .............................................................. 32
III
F85226
July, 2007
V0.25P
FINTEK [ FEATURE INTEGRATION TECHNOLOGY INC. ]
