DUAL 150MA HIGH PERFORMANCE MOBILE LDO
TM
IN USP6
FSP2151
FEATURES
180mV Typical Dropout with 150mA Load
±2.0%
Voltage Accuracy
High PSRR: 70dB@100Hz
Low noise output
Current Limit
Thermal Shutdown Protection
Short Circuit Protection
Very small USP6 Package
GENERAL DESCRIPTION
The dual LDO FSP2151 series of positive voltage
linear regulators feature high output voltage accuracy,
low quiescent current and low dropout voltage, making
them ideal for battery powered applications. The line
transient response and load transient response are
excellent. Their high PSRR make them useful in
applications where AC noise on the input power supply
must be suppressed. Space-saving USP6 package for
2ch LDOs is attractive for portable and handheld
applications. They have both thermal shutdown and a
current limit feature to prevent device failure under
extreme operating conditions. They are stable with an
output capacitance of 2.2uF or greater.
APPLICATIONS
Cellular Handsets
Portable Electronics, PDA
Wireless Devices, LAN
Computer Peripherals
Camera Module
GPS Receiver
PIN CONFIGURATION
(Bottom View)
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
Pin Name
EN2
VDD
EN1
GND
VOUT1
VOUT2
Pin Function
Enable pin for LDO2. Connect EN2 to IN or to a logic high for normal
operation, drive EN2 to G or a logic low to disable the regulator. Do not
leave EN2 floating.
Input Voltage. Bypass this pin with a 1µF capacitor connected to G, placed
as close to the IC as possible.
Enable pin for LDO1. Connect EN1 to IN or to a logic high for normal
operation, drive EN1 to G or a logic low to disable the regulator. Do not
leave EN1 floating.
Ground.
LDO1 Output. Bypass this pin with a 1µF capacitor connected to G. OUT1 is
actively discharged to G through 800Ω when disabled.
LDO2 Output. Bypass this pin with a 1µF capacitor connect to G. OUT2 is
actively discharged to G through 800Ω when disabled.
1/9
2007-7-4
FOSLINK [ FOSLINK SEMICONDUCTOR CO.,LTD ]
