1.5A LOW VOLTAGE LOW DROPOUT CMOS REGULATOR
FSP2160
APPLICATION INFORMATION
The FSP2160 family of low-dropout (LDO) regulators have several features that allow them to apply to a wide range
of applications. The family operates with very low input voltage (1.4V) and low dropout voltage (typically 150mV at
full load), making it an efficient stand-alone power supply or post regulator for battery or switch mode power supplies.
The 1.5A output current make the FSP2160 family suitable for powering many microprocessors and FPGA supplies.
The FSP2160 family also has low output noise (typically 40µVRMS with 2.2µF output capacitor), making it ideal for
use in telecom equipment.
External Capacitor Requirements
A 2.2µF or larger ceramic input bypass capacitor, connected between VIN and GND and located close to the
FSP2160, is required for stability. A 1.0uF minimum value capacitor from VO to GND is also required. To improve
transient response, noise rejection, and ripple rejection, an additional 10µF or larger, low ESR capacitor is
recommended at the output. A higher-value, low ESR output capacitor may be necessary if large, fast-rise-time load
transients are anticipated and the device is located several inches from the power source, especially if the minimum
input voltage of 1.4 V is used.
Regulator Protection
The FSP2160 features internal current limiting, thermal protection and short circuit protection. During normal
operation, the FSP2160 limits output current to about 3A. When current limiting engages, the output voltage scales
back linearly until the over current condition ends. While current limiting is designed to prevent gross device failure,
care should be taken not to exceed the power dissipation ratings of the package. If the temperature of the device
exceeds 150°C, thermal-protection circuitry will shut down. Once the device has cooled down to approximately 50°C
below the high temp trip point, regulator operation resumes. The short circuit current of the FSP2160 is about 1A
when its output pin is shorted to ground.
Thermal Information
The amount of heat that an LDO linear regulator generates is:
P
D
=(V
IN
-V
O
)I
O
.
All integrated circuits have a maximum allowable junction temperature (T
J
max) above which normal operation is not
assured. A system designer must design the operating environment so that the operating junction temperature (T
J
)
does not exceed the maximum junction temperature (T
J
max). The two main environmental variables that a designer
can use to improve thermal performance are air flow and external heatsinks. The purpose of this information is to aid
the designer in determining the proper operating environment for a linear regulator that is operating at a specific
power level.
In general, the maximum expected power (P
D(max)
) consumed by a linear regulator is computed as:
Where:
V
I (avg)
is the average input voltage.
V
O(avg)
is the average output voltage.
I
O(avg)
is the average output current.
I
(Q
) is the quiescent current.
For most LDO regulators, the quiescent current is insignificant compared to the average output current; therefore,
the term V
I(avg)
xI
(Q)
can be neglected. The operating junction temperature is computed by adding the ambient
temperature (T
A
) and the increase in temperature due to the regulator's power dissipation. The temperature rise is
computed by multiplying the maximum expected power dissipation by the sum of the thermal resistances between
the junction and the case (R
θJC
), the case to heatsink (R
θCS
), and the heatsink to ambient (R
θSA
). Thermal
resistances are measures of how effectively an object dissipates heat. Typically, the larger the device, the more
surface area available for power dissipation so that the object's thermal resistance will be lower.
4/11
2007-12-6
FOSLINK [ FOSLINK SEMICONDUCTOR CO.,LTD ]
