5.0V, HcMOS SMD Osꢂiꢃꢃator with Standꢄy
RoHS compꢃiant / Pꢄ Free
Modeꢃ: F4101 SERꢁES
Rev. 1/23/2009
Page 1 of 2
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FEATURES
• 5.0V Operation
• HCMOS Output
• Standby Function
• Tape and Reel (2,000 pcs. STD)
• PART ꢀUMbER SElEcTꢁOꢀ Learn More - Internet Required
7.5 M ax
Frequency
Model
Frequency
Operating
Temperature
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
-40 ~ +85ºC
-10 ~ +70ºC
Part Number
Number Stability1
Range (MHz)
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 170.000
0.012 ~ 162.000
0.012 ~ 156.250
0.012 ~ 162.000
#4
#1
#3
±100PPM
±100PPM
±50PPM
±50PPM
±25PPM
±25PPM
±20PPM
F4101
F4101R
F4102
F4102R
F4103
F4103R*
F4104*
118-Frequency-xxxxx
119-Frequency-xxxxx
120-Frequency-xxxxx
121-Frequency-xxxxx
122-Frequency-xxxxx
123-Frequency-xxxxx
446-Frequency-xxxxx
Top
5.2 M ax
View
#2
Dot denotes
pin 1
1.5 M ax
• ElEcTRꢁcAl cHARAcTERꢁSTꢁcS
1.4±0.2
MAX (unless otherwise noted)
0.012 ~ 170.000 MHz
-55ºC ~ +125ºC
PARAMETERS
Frequency Range (Fo)
Storage Temperature Range (Tstg)
#1
#4
#2
#3
Bottom
View
2.6±0.2
Supply Voltage
Input Current
(Vdd)
(Idd)
5.0V ± 10%
5.08±0.1
0.012 ~ 32.000 MHz
32.000+ ~ 67.000 MHz
18mA
50mA
67.000+ ~ 125.000 MHz
125.000+ ~ 170.000 MHz
Output Symmetry (50% Vdd)
Rise Time (10% ~ 90% Vdd) (Tr)
0.012 ~ 79.999999 MHz
80.000 ~ 170.000 MHz
80mA
90mA
40% ~ 60%
Recommended
Solder Pad Layout
1.8±0.1
5nS
4nS
2.0±0.1
Fall Time (90% ~ 10% Vdd) (Tf)
0.012 ~ 79.999999 MHz
80.000 ~ 170.000 MHz
4.2±0.1
5nS
4nS
5.08±0.1
Output Voltage
(Vol)
10% Vdd
90% Vdd Min
2mA Min
-2mA Min
15pF
(Voh)
Output Current
(Iol)
Pin Connections
(Ioh)
#1 E/D
#2 G ND #4 VDD
#3 O utput
Output Load
(HCMOS)
Standby Current
Start-up Time
10µA
10mS
150nS
10mS
All dim ensions are in m illim eters
(Ts)
Output Disable Time 2
Output Enable Time 2
1 Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, ag-
ing, shock, and vibration. *Excludes shock/vibration.
2 An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
Note: A 0.01µF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to
minimize power supply line noise.
Drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may
vary. All specifications subject to change without notice.
• EꢀAblE / DꢁSAblE FUꢀcTꢁOꢀ
OUTPUT (Pin 3)
INH (Pin 1)
OPEN 2
ACTIVE
ACTIVE
High Z
'1' Level Vih ≥ 70% Vdd
'0' Level Vil ≤ 30% Vdd
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