HcMOS 5x3.2mm 3.3V SMD Osꢀiꢁꢁator
RoHS compꢁiant / Pꢂ Free
Modeꢁ: F530l SERIES
Rev. 5/7/2009
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XpressO® Equivalent
OPTIONS
• 5.0V (F550L) Version Available
FEATuRES
• 3.3V Operation
FXO-HC53
• Standby Function
• Tape and Reel (1,000 pcs. STD)
Why XpressO?
Lower Cost, Faster Delivery, Low Jitter!
• PART NuMbER SElEcTIONLearn More - Internet Required
5.0 ± 0.2
Model
Number
F530L
Frequency
Operating
Frequency
# 4
# 3
Part Number
Stability1 Temperature (ºC) Range (MHz)
474-Frequency-xxxxx
475-Frequency-xxxxx
476-Frequency-xxxxx
550-Frequency-xxxxx
492-Frequency-xxxxx
636-Frequency-xxxxx
546-Frequency-xxxxx
±100PPM
±100PPM
±50PPM
±50PPM
±25PPM
±25PPM*
±20PPM*
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
-40 ~ +85
-10 ~ +70
1.544 ~ 155.520
1.544 ~ 155.520
1.544 ~ 155.520
1.544 ~ 155.520
1.544 ~ 155.520
1.544 ~ 155.520
1.544 ~ 77.760
Top
3.2 ± 0.2
View
F530LR
F535L
F535LR
F536L
F536LR
F538L
Dot denotes
pin 1
# 2
# 1
• ElEcTRIcAl cHARAcTERISTIcS
1.3 Max
MAX (unless otherwise noted)
PARAMETERS
1.544 ~ 155.520 MHz
-55ºC ~ +125ºC
3.3V ± 10%
Frequency Range (FO)
Storage Temperature Range (TSTG)
2.54±0.1
Supply Voltage
Input Current
(VDD)
(IDD)
# 2
# 1
15mA
20mA
25mA
1.544 ~ 32.000 MHz
32.000+ ~ 50.000 MHz
50.000+ ~ 67.000 MHz
Bottom
View
# 3
# 4
1.2
1.0
40mA
67.000+ ~ 155.520 MHz
40% ~ 60%
7nS
7nS
10% VDD
90% VDD Min
2mA Min
-2mA Min
15pF
10µA
10mS
150nS
10mS
Output Symmetry (50% VDD)
Rise Time (10% ~ 90% VDD) (TR)
Fall Time (90% ~ 10% VDD) (TF)
Recommended
Solder Pad Layout
Output Voltage
(VOL)
2.54
(VOH)
Output Current
(IOL)
(IOH)
1.29
Output Load
(HCMOS)
2.25
Standby Current
Start-up Time
(TS)
Output Disable Time 2
Output Enable Time 2
1.24
260ºC / 10 Seconds
1
Au
Reflow Soldering Temp
Moisture Sensitivity Level (MSL)
Termination Finish
1 Inclusive of 25ºC tolerance, operating temperature range, input voltage change, load change, aging,
shock, and vibration. *Excludes Shock/Vibration
Pin Connections
2 An internal pullup resistor from pin 1 to pin 4 allows active output if pin 1 is left open.
#1 E/D
#2 GND
#3 Oꢃtpꢃt
#4 V DD
Note: A 0.01µF bypass capacitor should be placed between VDD (Pin 4) and GND (Pin 2) to
minimize power supply line noise.
Drawing is for reference to critical specifications defined by size measurements.
Certain non-critical visual attributes, such as side castellations, reference pin shape, etc. may
vary. All specifications subject to change without notice.
• ENAblE / DISAblE FuNcTION
INH (Pin 1)
OPEN 2
OUTPUT (Pin 3)
ACTIVE
'1' Level VIH ≥ 70% VDD
'0' Level VIL ≤ 30% VDD
ACTIVE
High Z
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