Freescale Semiconductor
Technical Data
DSP56301
Rev. 10, 7/2006
DSP56301
24-Bit Digital Signal Processor
52
6
6
3
Memory Expansion Area
Triple
Timer
Host
Interface
X Data
Program
RAM
RAM
2048
×
24
4096
×
24 bits
bits
(Default)
(Default)
Y Data
RAM
2048
×
24
bits
(Default)
ESSI
SCI
Peripheral
Expansion Area
Address
Generator
Unit
Six-Channel
DMA Unit
24-Bit
Boot-
strap
ROM
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Power
Management
JTAG
OnCE™
24
YAB
XAB
PAB
DAB
External
Address
Bus
Switch
External
Bus
Interface
and
I-Cache
Control
The DSP56301 is intended
for general-purpose digital
signal processing,
particularly in multimedia
and telecommunication
applications, such as video
conferencing and cellular
telephony.
Address
14
Control
24
Internal
Data
Bus
Switch
EXTAL
Clock
XTAL
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODD/IRQD
MODC/IRQC
MODB/IRQB
MODA/IRQA
Program
Address
Generator
External
Data
Bus
Data
What’s New?
Rev. 10 includes the following
changes:
•
Removes all references to
Motorola. No specifications or
part numbers were changed.
Data ALU
24
×
24+56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
6
Figure 1.
DSP56301 Block Diagram
The DSP56301 is a member of the DSP56300 core family of programmable CMOS Digital Signal Processors
(DSPs). This family uses a high-performance, single clock cycle per instruction engine. Significant architectural
features of the DSP56300 core family include a barrel shifter, 24-bit addressing, instruction cache, and DMA. The
DSP56301 offers 80/100 MIPS using an internal 80/100 MHz clock at 3.0–3.6 volts. The DSP56300 core family
offers a rich instruction set and low power dissipation, as well as increasing levels of speed and power, enabling
wireless, telecommunications, and multimedia products.
© Freescale Semiconductor, Inc., 1996, 2006. All rights reserved.
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
