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DSP56321VL240 参数 Datasheet PDF下载

DSP56321VL240图片预览
型号: DSP56321VL240
PDF下载: 下载PDF文件 查看货源
内容描述: 24位数字信号处理器 [24-Bit Digital Signal Processor]
分类和应用: 数字信号处理器
文件页数/大小: 84 页 / 1566 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Freescale Semiconductor
Technical Data
DSP56321
Rev. 11, 2/2005
DSP56321
24-Bit Digital Signal Processor
3
16
6
6
Memory Expansion Area
Program
RAM
32 K
×
24 bits
or
31 K
×
24 bits
and
Instruction
Cache
1024
×
24 bits
PM_EB
SCI
Triple
Timer
HI08
ESSI
EFCOP
X Data
RAM
80 K
×
24 bits
Y Data
RAM
80 K
×
24 bits
PIO_EB
XM_EB
Address
Generation
Unit
Six Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
YM_EB
Peripheral
Expansion Area
External
Address
Bus
Switch
External
Bus
Interface
and
I - Cache
Control
External
Data
Bus
Switch
Power
Management
JTAG
OnCE™
18
Address
24-Bit
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
10
Control
The DSP56321 is intended
for applications requiring a
large amount of internal
memory, such as networking
and wireless infrastructure
applications. The onboard
EFCOP can accelerate
general filtering applications,
such as echo-cancellation
applications, correlation, and
general-purpose convolution-
based algorithms.
Internal
Data
Bus
Switch
24
Data
What’s New?
Rev. 11 includes the following
changes:
Adds lead-free packaging and
part numbers.
Clock
PLL
Generator
EXTAL
XTAL
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
Data ALU
24
×
24 + 56
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
5
DE
Figure 1.
DSP56321 Block Diagram
The Freescale DSP56321, a member of the DSP56300 DSP family, supports networking, security encryption, and
home entertainment using a high-performance, single-clock-cycle-per- instruction engine (DSP56000 code-
compatible), a barrel shifter, 24-bit addressing, an instruction cache, and a direct memory access (DMA) controller
(see
The DSP56321 offers 275 million multiply- accumulates per second (MMACS) performance, attaining 550
MMACS when the EFCOP is in use. It operates with an internal 275 MHz clock with a 1.6 volt core and
independent 3.3 volt input/output (I/O) power. By operating in parallel with the core, the EFCOP provides overall
enhanced performance and signal quality with no impact on channel throughput or total channel support. This
device is pin-compatible with the Freescale DSP56303, DSP56L307, DSP56309, and DSP56311.
© Freescale Semiconductor, Inc., 2001, 2005. All rights reserved.