ELECTRICAL CHARACTERISTICS
ELECTRICAL PERFORMANCE CURVES
t
R (SI)
< 10 ns
0.7V
DD
50%
t
F (SI)
< 10ns
5.0V
0.2V
DD
V
DD
= 5.0V
V
PWR
= 14V
SCLK
0
V
0H
R
L
= 26Ω
t
DLY(LH)
SO
(Low-to-High)
0.2V
DD
0.7V
DD
33298
V
0L
V
0H
CS
Under
Test
C
L
Output
SO
(High-to-Low)
t
VALID
0.7V
DD
t
R (SO)
t
F (SO)
t
DLY(HL)
0.2 V
DD
V
0L
SO (Low-to-High) is for an output with internal conditions such that
the low-to-high transition of CS causes the SO output to switch from
high to low.
C
L
represents the total capacitance of the test fixture and probe.
Figure 9. Switching Time Test Circuit
Figure 7. Valid Data Delay Time and
Valid Time Waveforms
V
DD
= 5.0V
tF(SI)
< 10 ns
0.7
VDD
5.0 V
0
t
R(SI)
CS
0.2VDD
V
PWR
= 11V
< 10 ns
90%
10%
tSO(EN)
90%
33298
CS
Under
Test
IL = 2.0A
(Output
ΟΝ)
Output
C
L
= 20 pF
SO
(High-to-Low)
tSO(DIS)
V
Tri-State
10%
t
SO(dis)
V0H
tSO(EN)
90%
tSO(DIS)
SO
(Low-to-High)
10%
V
Tri-State
C
L
represents the total capacitance of the test fixture and probe.
1. SO (high-to-low) waveform is for SO output with internal conditions such
that SO output is low except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state, e.g. open load.
2. SO (low-to-high) waveform is for SO output with internal conditions such
that SO output is high except when an output is disabled as a result of de-
tecting a circuit fault with CS in a High Logic state, e.g. shortened load.
Figure 10. Output Fault Unlatch Disable
Delay Test Circuit
Figure 8. Enable and Disable Time Waveforms
33298
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
