Paragraph
Number
TABLE OF CONTENTS
Page
Number
7
PULSE LENGTH D/A CONVERTERS
7.1
7.2
7.3
7.4
Miscellaneous register....................................................................................... 7–3
PLM clock selection........................................................................................... 7–4
PLM during STOP mode ................................................................................... 7–4
PLM during WAIT mode .................................................................................... 7–4
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
8.4
8.5
A/D converter operation..................................................................................... 8–1
A/D registers...................................................................................................... 8–3
Port D data register (PORTD)...................................................................... 8–3
A/D result data register (ADDATA) ............................................................... 8–3
A/D status/control register (ADSTAT)........................................................... 8–4
A/D converter during STOP mode..................................................................... 8–6
A/D converter during WAIT mode...................................................................... 8–6
Port D analog input............................................................................................ 8–6
9.1
Resets ............................................................................................................... 9–1
9.1.1
Power-on reset............................................................................................. 9–2
9.1.2
Miscellaneous register ................................................................................ 9–2
9.1.3
RESET pin ................................................................................................... 9–3
9.1.4
Computer operating properly (COP) watchdog reset .................................. 9–3
9.1.4.1
COP watchdog during STOP mode ....................................................... 9–4
9.1.4.2
9.1.5
Functions affected by reset.......................................................................... 9–5
9.2
Interrupts ........................................................................................................... 9–6
9.2.1
Interrupt priorities......................................................................................... 9–6
9.2.2
Nonmaskable software interrupt (SWI) ........................................................ 9–6
9.2.3
Maskable hardware interrupts ..................................................................... 9–7
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.4
Hardware controlled interrupt sequence.................................................... 9–11
Freescale
iv
TABLE OF CONTENTS
MC68HC05B6
Rev. 4.1
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
