Freescale Semiconductor, Inc.
5.1.6 CONFIG Register
CONFIG — Configuration Control Register
$003F
Bit 7
6
0
0
5
0
0
4
0
0
3
0
0
2
NOCOP
—
1
ROMON
—
Bit 0
0
0
0
0
RESET:
Bits [7:4] and 0 — Not implemented
Always read zero
NOCOP — COP System Disable
This bit is cleared out of reset in normal modes, enabling the COP system. It is set out
of reset in special modes. NOCOP is writable once in normal modes and at any time
in special modes.
0 = The COP system is enabled as the MCU comes out of reset.
1 = The COP system is disabled and does not generate system resets.
ROMON — Enable On-Chip ROM
Refer to SECTION 4 OPERATING MODES AND ON-CHIP MEMORY.
5.2 Effects of Reset
When a reset condition is recognized, the internal registers and control bits are forced
to an initial state. Depending on the cause of the reset and the operating mode, the
reset vector can be fetched from any of six possible locations. Refer to Table 5-2.
Table 5-2 Reset Cause, Reset Vector, and Operating Mode
Cause of Reset
POR or RESET Pin
Normal Mode Vector
$FFFE, FFFF
Special Test or Bootstrap
$BFFE, BFFF
Clock Monitor Failure
$FFFC, FFFD
$BFFC, $BFFD
COP Watchdog Time-out
$FFFA, FFFB
$BFFA, BFFB
These initial states then control on-chip peripheral systems to force them to known
startup states, as follows:
5.2.1 CPU
After reset, the CPU fetches the restart vector from the appropriate address during the
first three cycles, and begins executing instructions. The stack pointer and other CPU
registers are indeterminate immediately after reset; however, the X and I interrupt
mask bits in the condition code register (CCR) are set to mask any interrupt requests.
Also, the S bit in the CCR is set to inhibit the STOP mode.
5.2.2 Memory Map
After reset, the INIT register is initialized to $00, putting the 192 bytes of RAM at loca-
tions $0040 through $00FF, and the control registers at locations $0000 through
$003F.
RESETS AND INTERRUPTS
5-4
TECHNICAL DATA
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