Revision History
Revision
Level
Page
Number(s)
Date
Description
15.7.2 ADC Clock Control Register — Changed “The ADC clock should
be set to between 500kHz and 2MHz” to “The ADC clock should be set
to between 500kHz and 1MHz”
254
299
January 2007
4
Table 22-4 . DC Electrical Characteristics (5V) — Updated VOL values.
Table 22-6 . Oscillator Specifications (5V) and Table 22-10 . Oscillator
Specifications (3V) — Corrected internal oscillator clock frequency,
August 2005
3
301, 305
fICLK. Updated crystal oscillator component values CL, C1, C2, RB, and
RS.
Added MC68HC908AP16/AP8 information throughout.
—
Section 10. Monitor ROM (MON) — Corrected RAM address to $60.
167
October 2003
August 2003
2.5
2.4
Section 24. Electrical Specifications — Added run and wait IDD data for
8MHz at 3V.
421
Section 24. Electrical Specifications — Updated stop IDD data.
Removed MC68HC908AP16 references throughout.
417, 421
—
Table 1-2 . Pin Functions — Added footnote for VREG
.
30
5.3 Configuration Register 1 (CONFIG1) — Clarified LVIPWRD and
LVIREGD bits.
67
125
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode — Updated
BSC bit behavior.
July 2003
2.3
10.5 ROM-Resident Routines — Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
168–193
Figure 12-2 . Timebase Control Register (TBCR) — Corrected register
address.
207
415
101
415
Section 24. Electrical Specifications — Updated.
Updated for fNOM = 125kHz and filter components
in CGM section.
May 2003
2.2
Updated electricals.
MC68HC908AP Family Data Sheet, Rev. 4
4
Freescale Semiconductor
FREESCALE [ Freescale ]
