Freescale Semiconductor, Inc.
Technical Data — MC68HC908AS60
Section 11. Configuration Register (CONFIG-1)
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181
11.2 Introduction
This section describes the configuration register (CONFIG-1), which
contains bits that configure these options:
• Resets caused by the low-voltage inhibit (LVI) module
• Power to the LVI module
• LVI enabled during stop mode
• Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)
• Computer operating properly (COP) module
• STOP instruction enable/disable
11.3 Functional Description
The configuration register is a write-once register. Out of reset, the
configuration register will read the default value. Once the register is
written, further writes will have no effect until a reset occurs.
NOTE: If the LVI module and the LVI reset signal are enabled, a reset occurs
when VDD falls to a voltage, LVITRIPF, and remains at or below that level
for at least nine consecutive CPU cycles. Once an LVI reset occurs, the
MCU remains in reset until VDD rises to a voltage, LVITRIPR
.
MC68HC908AS60 — Rev. 1.0
Technical Data
Configuration Register (CONFIG-1)
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