Revision History
Date
Revision
Level
Description
be set to between 500kHz and 2MHz” to “The ADC clock should be set
Table 22-4 . DC Electrical Characteristics (5V)
— Updated V
OL
values.
August 2005
3
Table 22-6 . Oscillator Specifications (5V)
and
Table 22-10 . Oscillator
Specifications (3V)
— Corrected internal oscillator clock frequency,
f
ICLK
. Updated crystal oscillator component values C
L
, C
1
, C
2
, R
B
, and
October 2003
2.5
Section 10. Monitor ROM (MON)
— Corrected RAM address to $60.
Section 24. Electrical Specifications
— Added run and wait I
DD
data for
8MHz at 3V.
August 2003
2.4
— Updated stop I
DD
data.
Table 1-2 . Pin Functions
— Added footnote for V
REG
.
5.3 Configuration Register 1 (CONFIG1)
— Clarified LVIPWRD and
LVIREGD bits.
July 2003
2.3
Section 8. Clock Generator Module (CGM), 8.7.2 Stop Mode
— Updated
BSC bit behavior.
10.5 ROM-Resident Routines
— Corrected data size limits and control
byte size for EE_READ and EE_WRITE.
Figure 12-2 . Timebase Control Register (TBCR)
— Corrected register
address.
Section 24. Electrical Specifications
— Updated.
Updated for f
NOM
= 125kHz and filter components
in CGM section.
Updated electricals.
Page
Number(s)
254
January 2007
4
301, 305
167
421
417, 421
30
67
125
168–193
207
415
101
415
May 2003
2.2
MC68HC908AP Family Data Sheet, Rev. 4
4
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
