Section Number
Title
Page
Chapter 14
Serial Peripheral Interface (S08SPIV3)
14.1 Introduction ...................................................................................................................................235
14.1.1 Features ...........................................................................................................................237
14.1.2 Block Diagrams ..............................................................................................................237
14.1.3 SPI Baud Rate Generation ..............................................................................................239
14.2 External Signal Description ..........................................................................................................240
14.2.1 SPSCK — SPI Serial Clock ............................................................................................240
14.2.2 MOSI — Master Data Out, Slave Data In ......................................................................240
14.2.3 MISO — Master Data In, Slave Data Out ......................................................................240
14.2.4 SS — Slave Select ...........................................................................................................240
14.3 Modes of Operation .......................................................................................................................241
14.3.1 SPI in Stop Modes ..........................................................................................................241
14.4 Register Definition ........................................................................................................................241
14.4.1 SPI Control Register 1 (SPIC1) ......................................................................................241
14.4.2 SPI Control Register 2 (SPIC2) ......................................................................................242
14.4.3 SPI Baud Rate Register (SPIBR) ....................................................................................243
14.4.4 SPI Status Register (SPIS) ..............................................................................................244
14.4.5 SPI Data Register (SPID) ................................................................................................245
14.5 Functional Description ..................................................................................................................246
14.5.1 SPI Clock Formats ..........................................................................................................246
14.5.2 SPI Interrupts ..................................................................................................................249
14.5.3 Mode Fault Detection .....................................................................................................249
Chapter 15
Timer/PWM (S08TPMV3)
15.1 Introduction ...................................................................................................................................251
15.2 Features .........................................................................................................................................251
15.3 TPMV3 Differences from Previous Versions ................................................................................253
15.3.1 Migrating from TPMV1 ..................................................................................................255
15.3.2 Features ...........................................................................................................................256
15.3.3 Modes of Operation ........................................................................................................256
15.3.4 Block Diagram ................................................................................................................257
15.4 Signal Description .........................................................................................................................259
15.4.1 Detailed Signal Descriptions ...........................................................................................259
15.5 Register Definition ........................................................................................................................263
15.5.1 TPM Status and Control Register (TPMxSC) ................................................................263
15.5.2 TPM-Counter Registers (TPMxCNTH:TPMxCNTL) ....................................................264
15.5.3 TPM Counter Modulo Registers (TPMxMODH:TPMxMODL) ....................................265
15.5.4 TPM Channel n Status and Control Register (TPMxCnSC) ..........................................266
15.5.5 TPM Channel Value Registers (TPMxCnVH:TPMxCnVL) ..........................................268
15.6 Functional Description ..................................................................................................................269
MC9S08AC60 Series Data Sheet, Rev. 2
16
Freescale Semiconductor
FREESCALE [ Freescale ]
