Revision History
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The following revision history table summarizes changes contained in this document.
Revision
Number
1.0
1.1
1.2
1.3
1.4
1.5
Revision
Date
4/25/2003
Initial release
Description of Changes
Electricals change, appendix A only
Electricals change, appendix A only
10/2/2003
10/29/2003
11/12/2003
Added module version table; clarifications
Fixed typos and made corrections and clarifications
Added 1-MHz I
DD
values to Electricals, appendix A
Changed format of register names to enable reuse of code (from SCIBD to SCI1BD, even when
only one instance of a module on a chip)
Added new device: MC9S08GT16 to book. Added new 48-pin QFN package to book. BKGDPE
description in Section 5 — changed PTD0 to PTG0. Changed typo in CPU section that listed
MOV instruction as being 6 cycles instead of 5 (Table
8-2).
Format to Freescale look-and-feel; Clarified RTI clock sources and other changes in Chapter 5;
updated ICG initialization examples; expanded descriptions of LOLS and LOCS bits in ICGS1;
updated ICG electricals
Table A-9
and added a figure
Minor changes to
Table 7-4, Table 7-5, Table A-9;
Clarifications in
Section 11.10.6, “SCI x Control Register 3 (SCIxC3)”, Section 11.7, “Interrupts
and Status Flags”, Section 11.8.1, “8- and 9-Bit Data Modes”,
PTG availability in 48-pin
package (see
Table 2-2)
2
2/10/2004
2.2
9/2/2004
2.3
12/01/2004
This product incorporates SuperFlash
®
technology licensed from SST.
Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
©
Freescale Semiconductor, Inc., 2004. All rights reserved.
MC9S08GB/GT Data Sheet, Rev. 2.3
4
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