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MC9S08LG32CLK 参数 Datasheet PDF下载

MC9S08LG32CLK图片预览
型号: MC9S08LG32CLK
PDF下载: 下载PDF文件 查看货源
内容描述: 8位HCS08中央处理单元(CPU)的 [8-bit HCS08 Central Processor Unit (CPU)]
分类和应用: 外围集成电路时钟
文件页数/大小: 50 页 / 2918 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08LG32
Rev. 7, 8/2009
MC9S08LG32 Series
Covers: MC9S08LG32 and
MC9S08LG16
MC9S08LG32
80-LQFP
Case 917A
14 mm × 14 mm
64-LQFP
Case 840F
10 mm × 10 mm
Features
48-LQFP
• 8-bit HCS08 Central Processor Unit (CPU)
Case 932
7 mm × 7mm
– Up to 40 MHz CPU at 5.5 V to 2.7 V across temperature
– On-chip in-circuit emulator (ICE) debug module containing
range of –40 °C to 85 °C and –40 °C to 105 °C
three comparators and nine trigger modes; eight deep FIFO
– HCS08 instruction set with added BGND instruction
for storing change-of-flow addresses and event-only data;
– Support for up to 32 interrupt/reset sources
debug module supports both tag and force breakpoints
• On-Chip Memory
• Peripherals
– 32 KB or 18 KB dual array flash; read/program/erase
LCD
— Up to 4 × 41 or 8 × 37 LCD driver with internal
over full operating voltage and temperature
charge pump.
– 1984 byte random access memory (RAM)
ADC
— Up to 16-channel, 12-bit resolution; 2.5
μs
– Security circuitry to prevent unauthorized access to
conversion time; automatic compare function; temperature
RAM and flash contents
sensor; internal bandgap reference channel; runs in stop3 and
• Power-Saving Modes
can wake up the system; fully functional from 5.5 V to 2.7 V
– Two low-power stop modes (stop2 and stop3)
SCI
— Full duplex non-return to zero (NRZ); LIN master
– Reduced-power wait mode
extended break generation; LIN slave extended break
– Peripheral clock gating register can disable clocks to
detection; wakeup on active edge
unused modules, thereby reducing currents
SPI
— Full-duplex or single-wire bidirectional;
– Low power on-chip crystal oscillator (XOSC) that can
double-buffered transmit and receive; master or slave mode;
be used in low-power modes to provide accurate clock
MSB-first or LSB-first shifting
source to real time counter and LCD controller
IIC
— With up to 100 kbps with maximum bus loading;
– 100
μs
typical wakeup time from stop3 mode
multi-master operation; programmable slave address;
• Clock Source Options
interrupt driven byte-by-byte data transfer; supports
– Oscillator (XOSC) — Loop-control Pierce oscillator;
broadcast mode and 10-bit addressing
crystal or ceramic resonator range of 31.25 kHz to
TPMx
— One 6 channel and one 2 channel; selectable input
38.4 kHz or 1 MHz to 16 MHz
capture, output compare, or buffered edge or center-aligned
– Internal Clock Source (ICS) — Internal clock source
PWM on each channel
module containing a frequency-locked-loop (FLL)
MTIM
— 8-bit counter with match register; four clock
controlled by internal or external reference; precision
sources with prescaler dividers; can be used for periodic
trimming of internal reference allows 0.2% resolution
wakeup
and 2% deviation over temperature and voltage; supports
RTC
— 8-bit modulus counter with binary or decimal based
bus frequencies from 1 MHz to 20 MHz.
prescaler; three clock sources including one external source;
• System Protection
can be used for time base, calendar, or task scheduling
– COP reset with option to run from dedicated 1 kHz
functions
internal clock or bus clock
KBI
— One keyboard control module capable of supporting
– Low-voltage warning with interrupt
8 × 8 keyboard matrix
– Low-voltage detection with reset
IRQ
— External pin for wakeup from low-power modes
– Illegal opcode detection with reset
• Input/Output
– Illegal address detection with reset
– 39, 53, or 69 GPIOs
– Flash and RAM protection
– 8 KBI and 1 IRQ interrupt with selectable polarity
• Development Support
– Hysteresis and configurable pullup device on all input pins;
– Single-wire background debug interface
configurable slew rate and drive strength on all output pins.
– Breakpoint capability to allow single breakpoint setting
during in-circuit debugging (plus two more breakpoints • Package Options
– 48-pin LQFP, 64-pin LQFP, and 80-pin LQFP
in on-chip debug module)
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009. All rights reserved.