Chapter 3 Port Integration Module (PIM9E256V1)
3.3.1.4
R
W
Reset
R
W
Reset
Port AD Reduced Drive Register (RDRAD)
7
6
5
4
3
2
1
0
RDRAD15
0
7
RDRAD14
0
6
RDRAD13
0
5
RDRAD12
0
4
RDRAD11
0
3
RDRAD10
0
2
RDRAD9
0
1
RDRAD8
0
0
RDRAD7
0
RDRAD6
0
RDRAD5
0
RDRAD4
0
RDRAD3
0
RDRAD2
0
RDRAD1
0
RDRAD0
0
Figure 3-5. Port AD Reduced Drive Register (RDRAD)
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
Table 3-4. RDRAD Field Descriptions
Field
Description
15:0
Reduced Drive Port AD
RDRAD[15:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
3.3.1.5
R
W
Reset
R
W
Reset
Port AD Pull Device Enable Register (PERAD)
7
6
5
4
3
2
1
0
PERAD15
0
7
PERAD14
0
6
PERAD13
0
5
PERAD12
0
4
PERAD11
0
3
PERAD10
0
2
PERAD9
0
1
PERAD8
0
0
PERAD7
0
PERAD6
0
PERAD5
0
PERAD4
0
PERAD3
0
PERAD2
0
PERAD1
0
PERAD0
0
Figure 3-6. Port AD Pull Device Enable Register (PERAD)
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
Table 3-5. PERAD Field Descriptions
Field
15:0
Pull Device Enable Port AD
PERAD[15:0] 0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Description
MC9S12E256 Data Sheet, Rev. 1.08
132
Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
