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MCF5275CVM166 参数 Datasheet PDF下载

MCF5275CVM166图片预览
型号: MCF5275CVM166
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的微处理器系列硬件规格 [Integrated Microprocessor Family Hardware Specification]
分类和应用: 外围集成电路微处理器
文件页数/大小: 44 页 / 1246 K
品牌: FREESCALE [ Freescale ]
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Documentation  
9
Documentation  
Documentation regarding the MCF5275 and their development support tools is available from a local  
Freescale distributor, a Freescale semiconductor sales office, the Freescale Literature Distribution Center,  
or through the Freescale web address at http://www.freescale.com/coldfire.  
10 Revision History  
Table 29 provides a revision history for this hardware specification.  
Table 29. Document Revision History  
Rev. No.  
Substantive Change(s)  
0
1
• Initial release.  
• Added Figure 6.  
1.1  
• Removed duplicate information in the module description sections. The information is all in the  
Signals Description Table.  
1.2  
• Removed Overview, Features, Signal Descriptions, Modes of Operation, and Address  
Multiplexing sections. This information can be found in the MCF5275 Reference Manual.  
• Removed list of documentation in Section 9, “Documentation.. An up-to-date list is always  
available on our web site.  
• Changed CLKOUT -> PSTCLK in Section 8.16, “Debug AC Timing Specifications.”  
Table 10: Update VDD spec from 1.35-1.65 to 1.4-1.6.  
Table 13: Timings B6a, B6b, B6c, B7, B7a, B9, B12 updated:  
B6a, B6b, B6c maximum changed from “0.5tCYC + 5” to “0.5tCYC + 5.5”  
B7, B7a minimum changed from “0.5tCYC + 1.5” to “0.5tCYC + 1.0”  
B9, B11 minimum changed from “1.5” to “1.0”  
1.3  
2
• Added Section 5.2.1, “Supply Voltage Sequencing and Separation Cautions.”  
• Added thermal characteristics for 196 MAPBGA in Table 8.  
• Updated package dimensions drawing, Figure 6.  
• Removed second sentence from Section 8.11.1, “MII Receive Signal Timing  
(FECn_RXD[3:0], FECn_RXDV, FECn_RXER, and FECn_RXCLK),and Section 8.11.2, “MII  
Transmit Signal Timing (FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),”  
regarding no minimum frequency requirement for TXCLK.  
• Removed third and fourth paragraphs from Section 8.11.2, “MII Transmit Signal Timing  
(FECn_TXD[3:0], FECn_TXEN, FECn_TXER, FECn_TXCLK),as this feature is not  
supported on this device.  
MCF5275 Integrated Microprocessor Family Hardware Specification, Rev. 2  
42  
Freescale Semiconductor  
Preliminary—Subject to Change Without Notice