Features
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Features
Key features are shown below.
• MPC603e series G2_LE core
— Superscalar architecture
— 760 MIPS at 400 MHz (-40 to +85
o
C)
— 16 k Instruction cache, 16 k Data cache
— Double precision FPU
— Instruction and Data MMU
— Standard and Critical interrupt capability
• SDRAM / DDR Memory Interface
— up to 132-MHz operation
— SDRAM and DDR SDRAM support
— 256-MByte addressing range per CS, two CS available
— 32-bit data bus
— Built-in initialization and refresh
• Flexible multi-function External Bus Interface
— Supports interfacing to ROM/Flash/SRAM memories or other memory mapped devices
— 8 programmable Chip Selects
— Non multiplexed data access using 8/16/32 bit databus with up to 26-bit address
— Short or Long Burst capable
— Multiplexed data access using 8/16/32 bit databus with up to 25-bit address
• Peripheral Component Interconnect (PCI) Controller
— Version 2.2 PCI compatibility
— PCI initiator and target operation
— 32-bit PCI Address/Data bus
— 33- and 66-MHz operation
— PCI arbitration function
• ATA Controller
— Version 4 ATA compatible external interface—IDE Disk Drive connectivity
• BestComm DMA subsystem
— Intelligent virtual DMA Controller
— Dedicated DMA channels to control peripheral reception and transmission
— Local memory (SRAM 16 kBytes)
• 6 Programmable Serial Controllers (PSC), configurable for the following:
— UART or RS232 interface
MPC5200 Data Sheet, Rev. 4
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Freescale Semiconductor
FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
