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MPC8313VRAFFB 参数 Datasheet PDF下载

MPC8313VRAFFB图片预览
型号: MPC8313VRAFFB
PDF下载: 下载PDF文件 查看货源
内容描述: 的PowerQUICC ™II Pro处理器硬件规格 [PowerQUICC™ II Pro Processor Hardware Specifications]
分类和应用: 外围集成电路时钟
文件页数/大小: 100 页 / 1203 K
品牌: FREESCALE [ FREESCALE SEMICONDUCTOR, INC ]
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Overview
1.6
USB Dual-Role Controller
The MPC8313E USB controller includes the following features:
• Supports USB on-the-go mode, which includes both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
• Compatible with
Universal Serial Bus Specification, Rev. 2.0
• Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
• Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
• Supports full-speed (12 Mbps), and low-speed (1.5 Mbps) operation. Low-speed operation is
supported only in host mode.
• Supports UTMI + low pin interface (ULPI) or on-chip USB 2.0 full-speed PHY
1.7
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The MPC8313E eTSECs include the following features:
• Two RGMII/SGMII/MII/RMII/RTBI interfaces
• Two controllers designed to comply with IEEE Std 802.3®, 802.3u®, 802.3x®, 802.3z®,
802.3au®, and 802.3ab®
• Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
• MII management interface for external PHY control and status
• Three-speed support (10/100/1000 Mbps)
• On-chip high-speed serial interface to external SGMII PHY interface
• Support for IEEE Std 1588™
• Support for two full-duplex FIFO interface modes
• Multiple PHY interface configuration
• TCP/IP acceleration and QoS features available
• IP v4 and IP v6 header recognition on receive
• IP v4 header checksum verification and generation
• TCP and UDP checksum verification and generation
• Per-packet configurable acceleration
• Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2®, PPPoE session, MPLS
stacks, and ESP/AH IP-security headers
• Transmission from up to eight physical queues.
• Reception to up to eight physical queues
MPC8313E PowerQUICC
II Pro Processor Hardware Specifications, Rev. 2.1
4
Freescale Semiconductor