Layout Practices
These cautions are necessary for the long-term reliability of the part. If they are violated, the electrostatic discharge
(ESD) protection diodes are forward-biased, and excessive current can flow through these diodes. If the system
power supply design does not control the voltage sequencing, the circuit shown Figure 4 can be added to meet these
requirements. The MUR420 Schottky diodes control the maximum potential difference between the external bus and
core power supplies on power up, and the 1N5820 diodes regulate the maximum potential difference on power
down.
VDDH
VDDL
MUR420
1N5820
Figure 4. Example Voltage Sequencing Circuit
9 Layout Practices
Each V pin on the MPC885/880 should be provided with a low-impedance path to the board’s supply. Each GND
DD
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive distinct groups
of logic on chip. The V power supply should be bypassed to ground using at least four 0.1 µF by-pass capacitors
DD
located as close as possible to the four sides of the package. Each board designed should be characterized and
additional appropriate decoupling capacitors should be used if required. The capacitor leads and associated printed
circuit traces connecting to chip V and GND should be kept to less than half an inch per capacitor lead. At a
DD
minimum, a four-layer board employing two inner layers as V and GND planes should be used.
DD
All output pins on the MPC885/880 have fast rise and fall times. Printed circuit (PC) trace interconnection length
should be minimized in order to minimize undershoot and reflections caused by these fast output switching times.
This recommendation particularly applies to the address and data buses. Maximum PC trace lengths of six inches
are recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to
the PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the V and GND circuits. Pull up all unused
DD
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins. For more information, please refer to the MPC885 User’s Manual, Section 14.4.3, “Clock
Synthesizer Power (V
, V
, V
)”.
DDSYN
SSSYN
SSSYN1
10 Bus Signal Timing
The maximum bus speed supported by the MPC885/880 is 80 MHz. Higher-speed parts must be operated in
half-speed bus mode (for example, an MPC885/880 used at 133 MHz must be configured for a 66 MHz bus). Table 7
shows the frequency ranges for standard part frequencies in 1:1 bus mode, and Table 8 shows the frequency ranges
for standard part frequencies in 2:1 bus mode.
MPC885/MPC880 Hardware Specifications, Rev. 3
15
Freescale Semiconductor
FREESCALE [ Freescale ]
