IEEE 1149.1 Electrical Specifications
Figure 36 provides the reset timing for the debug port configuration.
CLKOUT
R70
R82
R80
SRESET
R80
R81
R81
DSCK, DSDI
Figure 36. Reset Timing—Debug Port Configuration
11 IEEE 1149.1 Electrical Specifications
Table 15 provides the JTAG timings for the MPC885/880 shown in Figure 37 to Figure 40.
Table 15. JTAG Timing
All
Frequencies
Num
Characteristic
Unit
Min
Max
J82
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK cycle time
100.00
40.00
0.00
5.00
25.00
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
10.00
—
TMS, TDI data setup time
TMS, TDI data hold time
—
TCK low to TDO data valid
27.00
—
TCK low to TDO data invalid
0.00
—
TCK low to TDO high impedance
TRST assert time
20.00
—
100.00
40.00
—
TRST setup time to TCK low
—
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
50.00
50.00
50.00
—
—
—
50.00
50.00
—
MPC885/MPC880 Hardware Specifications, Rev. 3
44
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