Freescale Semiconductor
Technical Data Advance Information
DSP56309
Rev. 7, 2/2005
DSP56309
24-Bit Digital Signal Processor
16
6
6
3
Memory Expansion Area
Triple
Timer
HI08
ESSI
SCI
PrograM
RAM
20480
×
24
bits
(default)
PM_EB
X Data
RAM
7168
×
24
bits
(default)
XM_EB
Y Data
RAM
7168
×
24
bits
(default)
YM_EB
PIO_EB
Peripheral
Expansion Area
The DSP56309 is intended
for applications benefiting
from a large amount of
internal memory, such as
wireless infrastructure
applications.
Address
Generation
Unit
Six-Channel
DMA Unit
Bootstrap
ROM
YAB
XAB
PAB
DAB
24-Bit
18
External
Address
Bus
Address
Switch
External
Bus
13
Interface
and Inst.
Cache Control
Control
External
Data Bus
Switch
24
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
EXTAL
XTAL
Clock
Generator
PLL
2
RESET
PINIT/NMI
Program
Interrupt
Controller
Program
Decode
Controller
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Program
Address
Generator
What’s New?
Data
Rev. 7 includes the following
changes:
•
Adds lead-free packaging and
part numbers.
24
×
24 + 56
→
56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
Data ALU
Power
Management
JTAG
OnCE™
5
DE
Figure 1.
DSP56309 Block Diagram
The DSP56309 is a member of the DSP56300 core family of programmable CMOS DSPs. The DSP56300 core
includes a barrel shifter, 24-bit addressing, an instruction cache, and direct memory access (DMA). The DSP56309
offers 100 MMACS at 3.0–3.6 V using an internal 100 MHz clock. The large internal memory is ideal for wireless
infrastructure and wireless local-loop applications. The DSP56300 core family offers a new level of performance in
speed and power provided by its rich instruction set and low-power dissipation, thus enabling a new generation of
wireless, multimedia, and telecommunications products.
Note:
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 1996, 2005. All rights reserved.
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