818 Series
Digital Tuning &
Control Characteristics
8-Bit Programmable Filters
Digital Tuning Characteristics
Pin-Out Key
IN
Analog Input Signal
D7 Tuning Bit 7 (MSB)
D6 Tuning Bit 6
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D0 - D7), a latch strobe bit (C), and a transition
polarity bit (P).
OUT Analog Output Signal
GND Power and Signal Return
D5 Tuning Bit 5
"P"
"C"
Transition Polarity Bit
Tuning Strobe Bit
D4 Tuning Bit 4
D3 Tuning Bit 3
Filter tuning follows the tuning equation given below:
+Vs Supply Voltage, Positive
-Vs Supply Voltage, Negative
D2 Tuning Bit 2
fc = ( fmax/256 ) [ 1 + D7 x 27 + D6 x 26 + D5 x 25 + D4 x 24 + D3 x
23 + D2 x 22 + D1 x 21 + D0 x 20 ]
D1 Tuning Bit 1
Os
Optional Offset Adjustment
D0 Tuning Bit 0 (LSB)
NC
No Connect (Highpass Models)
where D1 - D7 = "0" or "1", and
OUT +Vs
-Vs
fmax = Maximum tuning frequency;
fc = corner frequency;
Minimum tunable frequency = fmax/256 (D0 thru D7 = 0);
D7
D6
D5
Minimum frequency step (Resolution) = fmax/256
D4
GND
D3
D2
D1
D0
Data Control Specifications
Data Control Lines
Functions
Latch Strobe (C)
Transition Polarity (P)
IN
Os/NC
P C
Data Control Modes
Bottom View
Mode 1
P = 0; C = 0 frequency follows input codes
P = 0; C = 0⇑ frequency latched on rising edge
Bit
MSB ---
---
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LSB
Weight
Mode 2
P = 1; C = 1 frequency follows input codes
P = 1; C = 1⇓ frequency latched on falling edge
27
26
25
24
23
22
21
20
fc
Corner
Input Data Levels
(CMOS Logic)
Frequency
D7
D6
D5
D4
D3
D2
D1
D0
Input Voltage (Vs = 15 Vdc)
Low Level In
High Level In
0 Vdc min.
11 Vdc min.
4 Vdc max.
15 Vdc max.
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
fmax/256
fmax/128
fmax/64
fmax/32
fmax/16
fmax/8
Input Current
High Level In
Low Level In
- 10 -5 µA typ. -1 mA max.
+10 -5 µA typ. +1 µA max.
Input Capacitance
Latch Response
5 pF typ
7.5 pF max.
Data Set Up Time1 25 nS
Data Hold Time2
Strobe Pulse Width 80 nS min.
50 nS
Input Data Format
Positive Logic
Frequency Select Bits
fmax/4
Logic "1" = +Vs
Logic "0" = Gnd
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
256 : 1, Binary Weighted
fmax/2
Bit Weighting
D0
D7
fmax
Frequency Range
Notes:
1.Frequency data must be present before occurrence of strobe edge.
2.Frequency data must be present after occurrence of strobe edge.
2
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