D828 Series
8-Bit Programmable Filters
Digital Tuning Characteristics
The digital tuning interface circuits are a parallel set of eight
(8) 4053 CMOS switches which accept CMOS compatible
inputs for the eight tuning bits (D
0
- D
7
).
Filter tuning follows the tuning equation given below:
f
c
= ( f
max
/256 ) [ 1 + D
7
x 2 + D
6
x 2 + D
5
x 2 + D
4
x 2 +
D
3
x 2 + D
2
x 2 + D
1
x 2 + D
0
x 2 ]
where D
1
- D
7
= "0" or "1", and
f
max
= Maximum tuning frequency;
f
c
= corner frequency;
Minimum tunable frequency = f
max
/256 (D
0
thru D
7
= 0);
Minimum frequency step (Resolution) = f
max
/256
OUT +Vs -Vs
D
7
D
6
D
5
D
4
2.00
GND
D
3
D
2
D
1
D
0
+IN -IN Os
4
3
2
1
0
7
6
5
4
Digital Tuning &
Control Characteristics
Pin-Out Key
IN
OUT
GND
+Vs
-Vs
Os
Analog Input Signal
Analog Output Signal
Power and Signal Return
Supply Voltage, Positive
Supply Voltage, Negative
Offset Adjustment
D
7
Tuning
D
6
Tuning
D
5
Tuning
D
4
Tuning
D
3
Tuning
D
2
Tuning
D
1
Tuning
D
0
Tuning
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit
7 (MSB)
6
5
4
3
2
1
0 (LSB)
Data Input Specifications
Input Data Levels
(CMOS Logic)
4 Vdc max.
15 Vdc max.
-1
µA
max.
.
+1
µA
max.
7.5 pF max.
Input Voltage (Vs = 15 Vdc)
Low Level In
0 Vdc min.
High Level In
11 Vdc min.
Input Current
High Level In
Low Level In
Input Capacitance
Input Data Format
Positive Logic
Bit Weighting
D
0
D
7
Frequency Range
- 10
µA
typ.
-5
+10
µA
typ
.
5 pF typ
-5
MSB
2
7
---
2
6
---
2
5
---
2
4
---
2
3
---
2
2
---
2
1
LSB
2
0
Bit
Weight
Corner
Frequency
Frequency Select Bits
Logic "1" = +Vs
Logic "0" = Gnd
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
256 : 1, Binary Weighted
fc
D
7
0
0
0
0
0
0
0
0
1
D
6
0
0
0
0
0
0
0
1
1
D
5
0
0
0
0
0
0
1
1
1
D
4
0
0
0
0
0
1
1
1
1
D
3
0
0
0
0
1
1
1
1
1
D
2
0
0
0
1
1
1
1
1
1
D
1
0
0
1
1
1
1
1
1
1
D
0
0
1
1
1
1
1
1
1
1
f
max
/256
f
max
/128
f
max
/64
f
max
/32
f
max
/16
f
max
/8
f
max
/4
f
max
/2
fmax
2
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