R858 Series
Digital Tuning &
Range Switch
8-Bit Programmable Filters
Digital Tuning Characteristics
Control Characteristics
Pin-Out Key
The digital tuning interface circuits are two 4042 quad CMOS
latches which accept the following CMOS-compatible inputs:
eight tuning bits (D0 - D7), arrange selection bit (R), a latch
strobe bit (C), and a transition polarity bit (P).
IN
Analog Input Signal
D7 Tuning Bit 7 (MSB)
D6 Tuning Bit 6
D5 Tuning Bit 5
D4 Tuning Bit 4
D3 Tuning Bit 3
D2 Tuning Bit 2
D1 Tuning Bit 1
D0 Tuning Bit 0 (LSB)
OUT Analog Output Signal
GND Power and Signal Return
“P”
“C”
+Vs Supply Voltage, Positive
-Vs Supply Voltage, Negative
Os
R
Transition Polarity Bit
Tuning Strobe Bit
Filter tuning follows the tuning equation given below:
fc = ( fmax/256 ) [ 1 + D7 x 27 + D6 x 26 + D5 x 25 + D4 x 24 + D3 x
23 + D2 x 22 + D1 x 21 + D0 x 20 ]
Offset Adjustment
Range Switch Adjustment
where D1 - D7 = "0" or "1", and
fmax = Maximum tuning frequency;
OUT +Vs -Vs
R
fc = corner frequency;
Minimum tunable frequency = fmax/256 (D0 thru D7 = 0);
Minimum frequency step (Resolution) = fmax/256
D7
D6
D5
D4
GND
D3
D2
D1
D0
Data Input Specifications
Data Control Lines
2.00
Functions
Latch Strobe (C)
Transition Polarity (P)
Data Control Modes
Mode 1
P = 0; C = 0 frequency follows input codes
P = 0; C = 0› frequency latched on rising edge
4
IN Os
P
C
Mode 2
P = 1; C = 1 frequency follows input codes
Bottom View
P = 1; C = 1fl frequency latched on falling edge
Input Data Levels
(CMOS Logic)
Input Voltage (Vs = 15 Vdc)
Low Level In
0 Vdc min.
4 Vdc max.
15 Vdc max.
High Level In
11 Vdc min.
MSB ---
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LSB
Bit
Weight
Input Current
High Level In
- 10 -5 mA typ.
-1 mA max..
+1 mA max.
27
26
25
24
23
22
21
20
fc
Low Level In
+10 -5 mA typ.
Corner
Frequency
D7
0
0
0
0
0
0
0
0
1
D6
D5
D4
D3
D2
D1
D0
Input Capacitance
5 pF typ
7.5 pF max.
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
fmax/256
fmax/128
fmax/64
fmax/32
fmax/16
fmax/8
Latch Response
Data Set Up Time
1
25 nS
50 nS
2
Data Hold Time
Strobe Pulse Width 80 nS min.
Input Data Format
Frequency Select Bits
Positive Logic
Logic "1" = +Vs
Logic "0" = Gnd
Bit Weighting
D0
D7
(Binary-Coded)
LSB (least significant bit)
MSB (most significant bit)
fmax/4
Frequency Range
256 : 1, Binary Weighted
fmax/2
fmax
Notes:
1. Frequency data must be present before occurrence of strobe edge.
2. Frequency data must be present after occurrence of strobe edge.
2
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