Document Reference No.: FT_000367
UM232H Single Channel USB Hi-Speed FT232H Development Module
Datasheet Version 1.2
Clearance No.: FTDI# 198
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FT232H Features and Enhancement
3.1
Key Features
USB Hi-Speed to UART/FIFO Interface.
The FT232H provides a USB 2.0 Hi-Speed (480Mbits/s) to
flexible and configurable UART/FIFO Interfaces.
Functional Integration.
The FT232H integrates a USB protocol engine, which controls the physical
Universal Transceiver Macrocell Interface (UTMI) and handles all aspects of the USB 2.0 Hi-Speed interface.
The FT232H includes an integrated +1.8V/3.3V Low Drop-Out (LDO) regulator. It also includes 1Kbytes Tx
and Rx data buffers. The FT232H integrates the entire USB protocol on a chip with no firmware required.
MPSSE.
Multi-Protocol Synchronous Serial Engines (MPSSE), capable of speeds up to 30 Mbits/s, provides
flexible synchronous interface configurations.
FT1248 interface.
The FT232H supports a half-duplex FT1248 interface with a bi-directional data bus
interface that can be configured as 1, 2, 4 or 8-bits wide and this enables the flexibility to expand the
size of the data bus to 8 pins. The FT1248 interface provides flexible data communication between an
FT232H FT1248 slave and an external FT1248 master. The FT1248 interface consists of four signals
called
MIOSIO,
the bi-directional data lines between the FT232H and an external master controller,
SCLK
which is the external clock input for latching data in or out the device at frequency up to 30MHz,
SS_N
Slave select input
MISO
which is the Master In Slave Out is an output from the FT232H in FT1248 mode.
An external FT1248 master selects one of the FT1248 slave devices or enables the interface by pulling
the Slave select input (SS_N) to logic 0. The FT1248 mode can be configured via the EEPROM settings
with the free utility called FT_PROG which can be downloaded from the
page. For further
details about FT1248 mode, see FT232H datasheet and application note AN_167 FT1248 Parallel Serial
Interface Basics at the
Data Transfer rate.
The FT232H supports a data transfer rate up to 12 Mbaud when configured as an
RS232/RS422/RS485 UART interface or up to 40 Mbytes/second over a synchronous 245 parallel FIFO
interface or up to 8 Mbyte/Sec over an asynchronous 245 FIFO interface.
Latency Timer.
A feature of the driver used as a timeout to transmit short packets of data back to the PC.
The default is 16ms, but it can be altered between 0ms and 255ms.
Bus (ACBUS) functionality, signal inversion and drive strength selection.
There are 11 configurable
ACBUS I/O pins. These configurable options are:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
TXDEN
- transmit enable for RS485 designs.
PWREN#
- Power control for high power, bus powered designs.
TXLED#
- for pulsing an LED upon transmission of data.
RXLED#
- for pulsing an LED upon receiving data.
TX&RXLED#
- which will pulse an LED upon transmission OR reception of data.
SLEEP#
- indicates that the device going into USB suspend mode.
CLK30 / CLK15 / CLK7.5 -
30MHz, 15MHz and 7.5MHz clock output signal options.
TriSt-PU
– Input pulled up, not used
DRIVE 1
– Output driving high
DRIVE 0
- Output driving low
I/O mode
– ACBUS Bit Bang
The ACBUS pins can also be individually configured as GPIO pins, similar to asynchronous bit bang mode. It
is possible to use this mode while the UART interface is being used, thus providing up to 4 general purpose
I/O pins which are available during normal operation.
The ACBUS lines can be configured with any one of these input/output options by setting bits in the
external EEPROM
Multi-Purpose UART/FIFO Controllers.
The FT232H has one independent Serial/FIFO Controller. This
controls the UART data, 245 FIFO data, Fast Serial (opto isolation) or Bit-Bang mode which can be selected
by SETUP (SetBitMode) command. Each Multi-Purpose UART/FIFO Controller also contains an MPSSE
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