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V2DIP1-48 参数 Datasheet PDF下载

V2DIP1-48图片预览
型号: V2DIP1-48
PDF下载: 下载PDF文件 查看货源
内容描述: 设计,让使用VNC2-48Q IC设计快速发展 [Designed to allow rapid development of designs using the VNC2-48Q IC]
分类和应用:
文件页数/大小: 25 页 / 958 K
品牌: FTDI [ FUTURE TECHNOLOGY DEVICES INTERNATIONAL LTD. ]
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Document Reference No.: FT_000236  
V2DIP1-48 VNC2-48 Development Module Datasheet Version 1.01  
Clearance No.: FTDI# 153  
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Table of Contents  
1 Introduction............................................................................................ 1  
2 Features ................................................................................................. 3  
3 Pin Out and Signal Description ............................................................ 4  
3.1  
3.2  
3.3  
3.4  
3.5  
Module Pin Out ....................................................................................................4  
Pin Signal Description ........................................................................................6  
I/O Configuration Using The Jumper Pin Header .............................................8  
Default Interface I/O Pin Configuration..............................................................9  
UART Interface...................................................................................................10  
Signal Description UART Interface.............................................................................. 10  
Serial Peripheral Interface (SPI) .......................................................................11  
3.5.1  
3.6  
3.6.1  
Signal Description - SPI Slave ........................................................................................ 11  
Signal Description - SPI Master...................................................................................... 11  
Parallel FIFO Interface-Asynchronous Mode ..................................................12  
3.6.2  
3.7  
3.7.1  
Signal Description - Parallel FIFO Interface................................................................. 12  
Timing Diagram Asynchronous FIFO Mode Read and Write Cycle ..................... 13  
Parallel FIFO Interface-Synchronous Mode ....................................................14  
3.7.2  
3.8  
3.9  
3.8.1  
Timing Diagram Synchronous FIFO Mode Read and Write Cycle....................... 14  
Debugger Interface............................................................................................16  
3.9.1  
Signal Description - Debugger Interface ...................................................................... 16  
4 Firmware .............................................................................................. 17  
4.1  
4.2  
4.3  
Firmware Support..............................................................................................17  
Available Firmware............................................................................................17  
Firmware Upgrades...........................................................................................17  
5 External circuit Configuration ............................................................ 18  
5.1  
Adding a second USB Port...............................................................................18  
6 Mechanical Dimensions...................................................................... 19  
7 Schematic Diagram ............................................................................. 20  
8 Contact Information............................................................................. 21  
Appendix A References............................................................................................22  
Appendix B List of Figures and Tables...................................................................23  
List of Figures...............................................................................................................23  
List of Tables................................................................................................................23  
Appendix C Revision History...................................................................................24  
Copyright © 2010 Future Technology Devices International Limited  
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