MB15F78UL
s
PIN DESCRIPTION
Pin no.
TSSOP
1
2
3
4
5
6
BCC
19
20
1
2
3
4
Pin name I/O
OSC
IN
GND
fin
TX
Xfin
TX
GND
TX
V
CCTX
I
Descriptions
The programmable reference divider input pin. TCXO should be connected
with an AC coupling capacitor.
Prescaler input pin for the TX-PLL.
Connection to an external VCO should be via AC coupling.
Prescaler complimentary input pin for the TX-PLL section.
This pin should be grounded via a capacitor.
Power supply voltage input pin for the TX-PLL section (except for the charge
pump circuit) , the oscillator input buffer and the shift register.
Power saving mode control pin for the TX-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PS
TX
=
“H” ; Normal mode/PS
TX
=
“L” ; Power saving mode
Charge pump output pin for the TX-PLL section.
Lock detect signal output (LD) /phase comparator monitoring
output (fout) .The output signal is selected by LDS bit in the serial data.
LDS bit
=
“H” ; outputs fout signal/LDS bit
=
“L” ; outputs LD signal
Charge pump output pin for the RX-PLL section.
Power saving mode control pin for the RX-PLL section. This pin must be set
at “L” when the power supply is started up. (Open is prohibited.)
PS
RX
=
“H” ; Normal mode/PS
RX
=
“L” ; Power saving mode
Power supply voltage input pin for the RX-PLL section (except for the charge
pump circuit)
Prescaler complimentary input pin for the RX-PLL section.
This pin should be grounded via a capacitor.
Prescaler input pin for the RX-PLL.
Connection to an external VCO should be via AC coupling.
Load enable signal input pin (with the schmitt trigger circuit)
When LE is set “H”, data in the shift register is transferred to the
corresponding latch according to the control bit in a serial data.
Serial data input pin (with the schmitt trigger circuit)
Data is transferred to the corresponding latch (TX-ref. counter, TX-prog.
counter, RX-ref.counter, RX-prog.counter) according to the control bit in
a serial data.
Clock input pin for the 23-bit shift register (with a schmitt trigger circuit)
One bit of data is shifted into the shift register on a rising edge of the clock.
Ground pin for OSC input buffer and the shift register circuit.
I
I
Ground pin for the TX-PLL section.
I
7
8
9
10
11
12
13
5
6
7
8
9
10
11
PS
TX
Vp
TX
D
OTX
LD/fout
D
ORX
Vp
RX
PS
RX
Power supply voltage input pin for the TX-PLL charge pump.
O
O
O
Power supply voltage input pin for the RX-PLL charge pump.
I
14
15
16
17
12
13
14
15
V
CCRX
GND
RX
Xfin
RX
fin
RX
Ground pin for the RX-PLL section
I
I
18
16
LE
I
19
17
Data
I
20
18
Clock
I
3
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
