MB3793-27A
■ BLOCK DESCRIPTION
1. Comp. S
Comp. S is a comparator with hysteresis to compare the reference voltage with a voltage (VS) that is the result of
dividing the power voltage (VCC) by resistors 1 and 2. When VS falls below 1.24 V, a reset signal is output.
This function enables the MB3793 to detect an abnomality within 1 µs when the power is cut or falls abruptly.
2. Output circuit
The output circuit contains a RESET output control comparator that compares the voltage at the CTP pin to the
threshold voltage to release the RESET output if the CTP pin voltage exceeds the threshold value.
Since the reset (RESET) output buffer has CMOS organization, no pull-up resistor is needed.
3. Pulse generator
The pulse generator generates pulses when the voltage at the CK1 and CK2 clock pins changes to High from Low
level (positive-edge trigger) and exceeds the threshold voltage; it sends the clock signal to the watchdog timer.
4. Watchdog timer
The watchdog timer can monitor two clock pulses. Short-circuit the CK1 and CK2 clock pins to monitor a single
clock pulse.
5. Inhibition pin
The inhibition (INH) pin forces the watchdog timer on/off. When this pin is High level, the watchdog timer is stopped.
6. Logic circuit
The logic circuit contains flip-flops.
Flip-flop RSFF1 controls the charging and discharging of the power-on reset time setting capacitor (CTP).
Flip-flop RSFF2 turns on/off the circuit that accelerates charging of the power-on reset time setting capacitor
(CTP) at a reset. The RSFF2 operates only at a reset; it does not operate at a power-on reset when the power is
turned on.
4
FUJITSU [ FUJITSU ]
