MB3881
(Continued)
Parameter
Input offset voltage
Input bias current
Common mode input
voltage range
Voltage gain
Frequency bandwidth
Output voltage
Output source current
Output sink current
SCP Comp. block
(CH1 to CH4, SCP)
Sym-
bol
V
IO
I
B
V
CM
A
V
B
W
V
OH
V
OL
I
SOURCE
I
SINK
Pin No.
4, 5
6
5
4
4
4
4
4
4
4
DC
(Ta
=
+
25
°C,
VCC
=
9 V, VSS
=
4.4 V, VDD
=
5 V)
Value
Conditions
Unit
Min.
Typ.
Max.
FB
=
0.55 V
+IN =
0 V
FB
=
0.55 V
−15
−100
−50
0
60
1.1
60
0.97
0.77
−320
0.55
−200
0
−15
−50
FB
=
0.55 V
FB
=
0.55 V
0
−20
−10
75
1.2*
1.3
5
−2.0
140
1.00
0.80
−60
0.60
−40
0
−10
15
V
CC
−
0.9
200
−1.0
1.03
0.83
0.65
V
CC
−
1.8
15
mV
nA
nA
V
dB
MHz
V
mV
mA
µA
V
V
nA
V
nA
V
mV
nA
Error amplifier bolck
(CH8)
AV
=
0 dB
50, 53, 56, 57 CH1 to CH4
Threshold voltage
V
TH
62
Input bias current
Input offset voltage
Input bias current
Common mode input
voltage range
Input offset voltage
I
B
V
IO
I
B
V
CM
V
IO
I
B
46, 43, 40,
11, 37
60, 61
23, 17
60, 61
64
7
+IN =
1 V (CH7)
−IN =
0 V
−IN
(C)
=
0 V
FB
=
0.55 V
SCP Comp.
block (CH8 SCP)
SCP Comp. block
(CH5,CH6 SCP)
Input bias current
Common mode input
voltage range
V
CM
64
0
V
CC
−
0.9
V
PWM Comp. block
(CH1 to CH7)
Threshold voltage
V
T0
V
T100
50
50
Duty cycle
=
0%
Duty cycle
=
100%
0.9
1.0
1.73
1.83
V
V
Input bias current
I
DTC
48, 45, 42, 39, DTC
=
0.4 V
19, 13, 9
(CH1 to CH7)
−1.0
−0.3
µA
*: Standard design value.
(Continued)
12
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
