MB90092
s
PIN DESCRIPTION
Pin no.
Pin name
I/O
Circuit
type
Function
Test signal input pin. Input High level signal during normal operation.
This pin also can be used as a reset signal input pin by Low-level input
to the TEST pin. That is effective only after release of power-on reset.
This pin is a hysteresis input with an internal pull-up resistor.
Character interval signal output pin.
The output signal represents the character dot output interval.
Character/background internal signal output pin.
During internal synchronization control operation, the output signal rep-
resents the character, character background, line background, or screen
background output interval.
Color signal output pins.
These pins output the character, character background, line back-
ground, and screen background color signals.
Chip select pin.
For serial transfer, set this pin to the Low level.
This pin is also used to release a power-on reset.
The pin is a hysteresis input with an internal pull-up resistor.
Shift clock input pin for serial transfer.
This pin is a hysteresis input with an internal pull-up resistor.
Serial data input pin.
The pin is a hysteresis input with an internal pull-up resistor.
External horizontal sync signal input pin.
Input negative logic signal.
This pin can also serve as a composite sync signal input pin depending
on the internal register setting.
The pin is a hysteresis input with an internal pull-up resistor.
External vertical sync signal input pin.
Input negative logic signal.
Input to this pin is disabled when composite sync signal input has been
selected by setting the internal register. The pin is a hysteresis input with
an internal pull-up resistor.
Horizontal sync signal output pin.
This pin can also output composite sync signals depending on the inter-
nal register setting.
The pin outputs the signal (FSC) resulting from dividing the 4FSC clock
frequency by setting the TEST pin to the Low level.
Vertical sync signal output pin.
This pin is fixed at the High level when composite sync signal output has
been selected by setting the internal register.
The pin outputs the dot clock oscillator signal when the TEST pin goes
into Low.
Vertical blanking interval signal output pin.
This pin outputs the Low-level signal in the vertical blanking interval.
1
TESTI
I
B
2
VOC
O
C
3
VOB
O
C
5
6
7
B
R
G
O
C
8
CS
I
B
9
10
SCLK
SIN
I
I
B
B
12
EXHSYN
I
B
13
EXVSYN
I
B
14
HSYNC
O
C
15
VSYNC
O
C
16
VBLNK
O
C
(Continued)
5
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
