MBM29F040C-55/-70/-90
Write Operation Status
Table 6 Hardware Sequence Flags
DQ7
Status
DQ6
DQ5
0
DQ3
0
DQ2
1
Embedded Program Algorithm
Embedded Erase Algorithm
DQ7
0
Toggle
Toggle
0
1
Toggle
Erase Suspend Read
(Erase Suspended Sector)
1
1
0
Data
0
0
Data
0
Toggle
Data
In Progress
Erase
Erase Suspend Read
Suspended
Data
DQ7
Data
(Non-Erase Suspended Sector)
Mode
Erase Suspend Program
Non-Erase Suspended Sector)
Toggle
(Note 1)
1
(Note 2)
Embedded Program Algorithm
DQ7
0
Toggle
Toggle
1
1
0
1
1
Program/Erase in Embedded Erase Algorithm
N/A
Exceeded
Time Limits
Erase
Erase Suspend Program
Suspended
DQ7
Toggle
1
0
N/A
(Non-Erase Suspended Sector)
Mode
Notes:1. Performing successive read operations from any address will cause DQ6 to toggle.
2. Reading the byte address being programmed while in the erase-suspend program mode will indicate logic
“1” at the DQ2 bit. However, successive reads from the erase-suspended sector will cause DQ2 to toggle.
3. DQ0 and DQ1 are reserve pins for future use. DQ4 is for Fujitsu internal use only.
DQ7
Data Polling
TheMBM29F040CdevicefeaturesDataPollingasamethodtoindicatetothehostthattheEmbeddedAlgorithms
areinprogressorcompleted. DuringtheEmbeddedProgramAlgorithmanattempttoreadthedevicewillproduce
the compliment of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt
to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an
attempttoreadthedevicewillproducea“0”attheDQ7 output.UponcompletionoftheEmbeddedEraseAlgorithm
an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data Polling (DQ7) is shown
in Figure 15.
For chip erase, and sector erase the Data Polling is valid after the rising edge of the sixth WE pulse in the six
write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase
WE pulse. Data Polling must be performed at sector address within any of the sectors being erased and not a
protected sector. Otherwise, the status may not be valid. Once the Embedded Algorithm operation is close to
being completed, the MBM29F040C data pins (DQ7) may change asynchronously while the output enable (OE)
is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then
that byte’s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may
read the status or valid data. Even if the device has completed the Embedded Algorithm operation and DQ7 has
a valid data, the data outputs on DQ0 to DQ6 may be still invalid. The valid data on DQ0 to DQ7 will be read on
the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase
Algorithm, or sector erase time-out. (See Table 6.)
See Figure 9 for the Data Polling timing specifications and diagrams.
15
FUJITSU [ FUJITSU ]
