MBM29F200TC
-55/-70/-90
/MBM29F200BC
-55/-70/-90
s
GENERAL DESCRIPTION
The MBM29F200TC/BC is a 2M-bit, 5.0 V-only Flash memory organized as 256K bytes of 8 bits each or 128K
words of 16 bits each. The MBM29F200TC/BC is offered in a 48-pin TSOP and 44-pin SOP packages. This
device is designed to be programmed in-system with the standard system 5.0 V V
CC
supply. 12.0 V V
PP
is not
required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers.
The standard MBM29F200TC/BC offers access times 55 ns and 90 ns allowing operation of high-speed
microprocessors without wait states. To eliminate bus contention the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls.
The MBM29F200TC/BC is pin and command set compatible with JEDEC standard. Commands are written to
the command register using standard microprocessor write timings. Register contents serve as input to an
internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase operations. Reading data out of the devices is similar
to reading from12.0 V Flash or EPROM devices.
The MBM29F200TC/BC is programmed by executing the program command sequence. This will invoke the
Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths
and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.5 seconds.
Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase
Algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed
before executing the erase operation. During erase, the device automatically times the erase pulse widths and
verifies proper cell margin.
A sector is typically erased and verified in 1.0 second (if already completely preprogrammed.).
The devices also features a sector erase architecture. The sector mode allows each sector to be erased and
reprogrammed without affecting other sectors. The MBM29F200TC/BC is erased when shipped from the factory.
The devices features single 5.0 V power supply operation for both read and write functions. Internally generated
and regulated voltages are provided for the program and erase operations. A low V
CC
detector automatically
inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ
7
,
by the Toggle Bit feature on DQ
6
, or the RY/BY output pin. Once the end of a program or erase cycle has been
completed, the device internally resets to the read mode.
Fujitsu’s Flash technology combines years of EPROM and E
2
PROM experience to produce the highest levels
of quality, reliability, and cost effectiveness. The MBM29F200TC/BC memory electrically erase the entire chip
or all bits within a sector simultaneously via Fowler-Nordhiem tunneling. The bytes/words are programmed one
byte/word at a time using the EPROM programming mechanism of hot electron injection.
3
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
