FUJITSU SEMICONDUCTOR
DATA SHEET
DS05-20864-3E
FLASH MEMORY
CMOS
4M (512K
×
8) BIT
MBM29LV004TC
-70/-90/-12
/MBM29LV004BC
-70/-90/-12
s
FEATURES
• Single 3.0 V read, program, and erase
Minimizes system level power requirements
• Compatible with JEDEC-standard commands
Uses same software commands as E
2
PROMs
• Compatible with JEDEC-standard world-wide pinouts
40-pin TSOP(I) (Package suffix: PTN – Normal Bend Type, PTR – Reversed Bend Type)
40-pin SON (Package suffix: PNS)
• Minimum 100,000 program/erase cycles
• High performance
70 ns maximum access time
• Sector erase architecture
One 16K byte, two 8K bytes, one 32K byte, and seven 64K bytes
Any combination of sectors can be concurrently erased. Also supports full chip erase
• Boot Code Sector Architecture
T = Top sector
B = Bottom sector
• Embedded Erase
TM
Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded Program
TM
Algorithms
Automatically writes and verifies data at specified address
• Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready/Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode
• Low V
CC
write inhibit
≤
2.5 V
• Erase Suspend/Resume
Suspends the erase operation to allow a read data in another sector within the same device
• Sector protection
Hardware method disables any combination of sectors from program or erase operations
• Sector Protection Set function by Extended sector protection command
• Temporary sector unprotection
Temporary sector unprotection via the RESET pin
Embedded Erase
TM
and Embedded Program
TM
are trademarks of Advanced Micro Devices, Inc.
FUJITSU [ FUJITSU COMPONENT LIMITED. ]
