NJ8821
DS3278-1.3
NJ8821
FREQUENCY SYNTHESISER (MICROPROCESSOR INTERFACE)
WITH RESETTABLE COUNTERS
The NJ8821 is a synthesiser circuit fabricated on the GPS
CMOS process and is capable of achieving high sideband
attenuation and low noise performance. It contains a reference
oscillator, 11-bit programmable reference divider, digital and
sample-and-hold comparators, 10-bit programmable ‘M’ counter,
7-bit programmable ‘A’ counter and the necessary control and
latch circuitry for accepting and latching the input data.
Data is presented as eight 4-bit words under external control
from a suitable microprocessor..
It is intended to be used in conjunction with a two-modulus
prescaler such as the SP8710 series to produce a universal
binary coded synthesiser.
The NJ8821 is available in Plastic DIL (DP) and Miniature
Plastic DIL (MP) packages, both with operating temperature
range of
230°C
to
170°C.
The NJ8821MA is available only in
Ceramic DIL package with operating temperature range of
240°C
to
185°C.
PDA
PDB
LD
F
IN
V
SS
V
DD
OSC IN
OSC OUT
D0
D1
1
2
3
4
5
20
19
18
17
16
CH
RB
MC
DS2
DS1
DS0
PE
NC
D3
D2
NJ8821
6
7
8
9
10
15
14
13
12
11
DP20, MP20
DG20
FEATURES
Fig.1 Pin connections - top view
s
s
s
s
Low Power Consumption
Microprocessor Compatible
High Performance Sample and Hold Phase Detector
>10MHz Input Frequency
ABSOLUTE MAXIMUM RATINGS
Supply voltage, V
DD
2V
SS
Input voltage
Open drain output, pin 3
All other pins
Storage temperature
Storage temperature
20·5V
to 7V
7V
V
SS
20·3V
to V
DD
10·3V
265°C
to
1150°C
(DG package, NJ8821MA)
255°C
to
1125°C
(DP and MP packages, NJ8821)
ORDERING INFORMATION
NJ8821 BA DP
Plastic DIL Package
NJ8821 BA MP
Miniature Plastic DIL Package
NJ8821 MA DG
Ceramic DIL Package
DATA SELECT INPUTS
DS0 DS1 DS2
15
PROGRAM
ENABLE (PE)
14
LATCH SELECT
LOGIC
16
17
TO
INTERNAL
LATCHES
f
r
RB
19
CH
20
OSC IN
OSC OUT
7
8
REFERENCE COUNTER
(11BITS)
42
SAMPLE/HOLD
PHASE
DETECTOR
FREQUENCY/
PHASE
DETECTOR
1
PDA
LATCH 6 LATCH 7 LATCH 8
2
D0
DATA
D1
INPUTS
D2
D3
9
10
11
12
PDB
3
V
SS
LOCK DETECT (LD)
LATCH 4 LATCH 5
LATCH 1 LATCH 2 LATCH 3
F
IN
4
‘A’ COUNTER
(7 BITS)
‘M’ COUNTER
(10 BITS)
f
v
V
DD
V
SS
6
CONTROL LOGIC
5
18
MODULUS
CONTROL
OUTPUT (MC)
Fig.2 Block diagram
GEC [ GENERAL ELECTRIC COMPANY ]
