GL424 SD/MMC Flash Card Controller
LIST OF TABLES
T
ABLE
3.1 - 46 PIN LQFN R
EGULATOR
I
NTERFACE
....................................................... 16
T
ABLE
3.2 - 54 PIN VFBGA R
EGULATOR
I
NTERFACE
.................................................... 16
T
ABLE
3.3 – D
IE
P
AD
R
EGULATOR
I
NTERFACE
................................................................ 16
T
ABLE
3.4 – 46 PIN LGA R
EGULATOR
I
NTERFACE
......................................................... 17
T
ABLE
3.5 – 51 PIN LGA R
EGULATOR
I
NTERFACE
......................................................... 17
T
ABLE
3.3 - 46 PIN LQFN C
ARD
I
NTERFACE
.................................................................. 18
T
ABLE
3.4 - 54 PIN VFBGA C
ARD
I
NTERFACE
............................................................... 18
T
ABLE
3.5 – D
IE
P
AD
C
ARD
I
NTERFACE
........................................................................... 19
T
ABLE
3.6 - 46 PIN LGA C
ARD
I
NTERFACE
..................................................................... 20
T
ABLE
3.7 - 51 PIN LGA C
ARD
I
NTERFACE
..................................................................... 20
T
ABLE
3.8 - 46 PIN LQFN F
LASH
I
NTERFACE
................................................................. 21
T
ABLE
3.9 - 54 PIN VFBGA F
LASH
I
NTERFACE
.............................................................. 21
T
ABLE
3.10 – D
IE
P
AD
F
LASH
I
NTERFACE
........................................................................ 22
T
ABLE
3.11 – 46 PIN LGA F
LASH
I
NTERFACE
................................................................. 23
T
ABLE
3.12 – 51 PIN LGA F
LASH
I
NTERFACE
................................................................. 23
T
ABLE
3.13 - 46 PIN LQFN S
YSTEM
I
NTERFACE
............................................................ 24
T
ABLE
3.14 - 54 PIN VFBGA S
YSTEM
I
NTERFACE
.......................................................... 24
T
ABLE
3.15 - D
IE
P
AD
S
YSTEM
I
NTERFACE
...................................................................... 25
T
ABLE
3.16 - 46 PIN LGA S
YSTEM
I
NTERFACE
............................................................... 26
T
ABLE
3.17 - 51 PIN LGA S
YSTEM
I
NTERFACE
............................................................... 26
T
ABLE
3.18 - 54 PIN VFBGA T
EST
I
NTERFACE
.............................................................. 27
T
ABLE
3.19 - D
IE
P
AD
T
EST
I
NTERFACE
........................................................................... 27
T
ABLE
4.1 - A
BSOLUTE
M
AXIMUM
R
ATINGS
.................................................................... 28
T
ABLE
4.2 - B
US
O
PERATING
C
ONDITIONS
....................................................................... 28
T
ABLE
4.3 - D.C. C
HARACTERISTICS
................................................................................ 28
T
ABLE
6.1- O
RDERING
I
NFORMATION
.............................................................................. 34
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