GL800AHU35 USB 2.0 UTMI Compliant Transceiver IP Core
3.2 Block Diagram
Data+
Data-
HS XCVR
Rcv
HS
DLL
Elasticity
Buffer
M
U
X
NRZI
Decoder
Bit
Unstuffer
Status/
Control
Xmit
Receive
State
Machine
Transmit
State
Machine
Rx
Register
Parallel
Rx Data
FS XCVR
Rcv
FS DLL
& Data
Recovery
Status/
Control
Xmit
NRZI
Encoder
Tx
Register
Parallel
Tx Data
Bit
Stuffer
CLK
Analog Front End
External
Crystal
Clock
Multiplier
Control
Logic
Control
Figure 3.2 - Block Diagram
1. HS XCVR
HS XCVR contains the low-level analog circuitry required to physically interface USB 2.0 signaling to the
USB DP/DM signal lines.
2. FS XCVR
FS XCVR includes the logic necessary to send and receive the FS data on USB.
3. Clock Multiplier
Clock Multiplier generates the internal clocks for the GL800HT25 USB 2.0 Transceiver and the CLK30
signal. All data transfer signals are synchronized with the CLK30 signal.
In HS mode there is one clock cycle per byte time. The frequency of clock does not change when the UTMI
is switched between HS to FS modes. In FS mode there are 5 clock cycles per FS bit time, typically 40
clock cycles per FS byte time. If a received byte contains a stuffed bit then the byte boundary can be
stretched to 45 clock cycles, and two stuffed bits would result in a 50 clock delay between bytes.
4. HS DLL
(High Speed Delay Line PLL)
DLL extracts clock and data from the data received over the USB 2.0 interface for reception by the Receive
Deserializer. The data output from the DLL is synchronous with the local clock.
©2000-2003 Genesys Logic Inc.—All rights reserved.
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