GL811E USB 2.0 to ATA/ATAPI Bridge Controller
CHAPTER 3
3.1 Pinouts
PIN ASSIGNMENT
DMACK_
AGND1
DIOW_
IORDY
INTRQ
DIOR_
TEST
CS0_
DA1
DA0
X1
26
36
35
34
33
32
31
30
29
28
27
DMARQ
IODD[0]
IODD[1]
IODD[2]
IODD[3]
DGND2
DVCC2
IODD[4]
IODD[5]
IODD[6]
IODD[7]
GPIO1
37
38
39
40
41
42
43
44
45
46
47
48
25
X2
24
23
22
21
20
AVCC1
RREF
AGND0
DMH
DMF
DPH
DPF
AVCC0
RPU
RESET#
DA2/SK
CS1_
GL811E
LQFP/TQFP - 48
19
18
17
16
15
14
13
10
11
IODD[15]
DGND1
IODD[10]
IODD[11]
IODD[12]
IODD[13]
Figure 3.1 - 48 Pin LQFP/TQFP Pinout Diagram
© 2000-2005 Genesys Logic Inc. - All rights reserved.
IODD[14]
IODD[8]
IODD[9]
CBLID_
GPIO7
DVCC1
12
1
2
3
4
5
6
7
8
9
Page 9
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