GL824/GL824C USB 2.0 On-The-Go Controller
LIST OF FIGURES
F
IGURE
3.1 - 208 P
IN
LQFP P
INOUT
D
IAGRAM
.............................................................12
F
IGURE
3.2
–
128 P
IN
LQFP P
INOUT
D
IAGRAM
.............................................................13
F
IGURE
4.1 - GL824 B
LOCK
D
IAGRAM
..........................................................................24
F
IGURE
5.1 - O
NE
B
YTE
R
ECEIVE
/T
RANSMIT
T
IMING
D
IAGRAM
(C
LOCK
O
PPOSITE
)...26
F
IGURE
5.2 - O
NE
B
YTE
R
ECEIVE
/T
RANSMIT TIMING DIAGRAM
(
CLOCK NORMAL
).......26
F
IGURE
5.3 - C
ONTINUES
R
ECEIVE
/T
RANSMIT
D
ATA TIMING DIAGRAM
(
CLOCK
OPPOSITE
) ......................................................................................................................26
F
IGURE
5.4 - C
ONTINUES
R
ECEIVE
/T
RANSMIT
D
ATA TIMING DIAGRAM
(
CLOCK
NORMAL
)........................................................................................................................26
F
IGURE
5.5 - D
ATA
F
RAME
.............................................................................................27
F
IGURE
5.6 - C
OMMAND
W
RITE
T
IMING
D
IAGRAM
.......................................................28
F
IGURE
5.7 - S
TATUS
R
EAD
T
IMING
D
IAGRAM
..............................................................28
F
IGURE
5.8 - D
ATA
W
RITE
T
IMING
D
IAGRAM
...............................................................29
F
IGURE
5.9 - D
ATA
R
EAD
T
IMING
D
IAGRAM
.................................................................29
F
IGURE
6.1
–
E
MBEDDED
PMOS S
WITCH
A
RCHITECTURE
............................................32
F
IGURE
6.2
–
I-V C
URVE OF
PMOS S
WTICH
.................................................................33
F
IGURE
6.3
–
T
RANSIENT
A
NALYSIS OF
PMOS S
WITCH
................................................34
F
IGURE
6.4
–
T
IMING
D
IAGRAM OF
E
XTERNAL
F
LASH
..................................................34
F
IGURE
6.5 - T
IMING
D
IAGRAM OF
S
MART
M
EDIA
.........................................................35
F
IGURE
6.6 - T
IMING
D
IAGRAM OF X
D-P
ICTURE
...........................................................36
F
IGURE
6.7 - T
IMING
D
IAGRAM OF
M
EMORY
S
TICK
......................................................37
F
IGURE
6.8 - T
IMING
D
IAGRAM OF
M
EMORY
S
TICK
PRO..............................................37
F
IGURE
6.9 - T
IMING
D
IAGRAM OF
SD / MMC ..............................................................37
F
IGURE
6.10 - T
IMING
D
IAGRAM OF
C
OMPACT
F
LASH
...................................................38
F
IGURE
6.11 - T
IMING
D
IAGRAM OF
R
ESET
...................................................................39
F
IGURE
6.12
–
R
EGISTER
T
RANSFERS
T
IMING
...............................................................41
F
IGURE
6.13 - I
NITIATING A
M
ULTIWORD
DMA D
ATA
B
URST
......................................43
F
IGURE
6.14 - S
USTAINING A
M
ULTIWORD
DMA D
ATA
B
URST
.....................................44
F
IGURE
6.15 - D
EVICE
T
ERMINATING A
M
ULTIWORD
DMA D
ATA
B
URST
....................44
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Genesys Logic Inc. - All rights reserved.
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