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GS1545 参数 Datasheet PDF下载

GS1545图片预览
型号: GS1545
PDF下载: 下载PDF文件 查看货源
内容描述: 高清晰度电视串行数字均衡接收机 [HDTV Serial Digital Equalizing Receiver]
分类和应用: 电视接收机
文件页数/大小: 19 页 / 263 K
品牌: GENNUM [ GENNUM CORPORATION ]
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HD-LINX
GS1545
HDTV Serial Digital
Equalizing Receiver
DATA SHEET
FEATURES
• SMPTE 292M compliant
• 1.485 and 1.485/1.001Gb/s operation
• integrated adaptive cable equalizer
• integrated adjustment-free reclocker
• 1:20 serial to parallel conversion
• selectable reclocked serial output
• analog/digital input MUX
• carrier detect
• LOCK detect
• input jitter indicator (IJI)
• cable length indication
• maximum cable length adjust
• 20 bit output
• 74.25MHz or 74.25/1.001MHz clock output
• Pb-free and Green
• single +5.0V power supply
• minimal component count for HD SDI receive
solutions
APPLICATIONS
SMPTE 292M Serial Digital Interfaces for Video Cameras,
Camcorders, VTRs, Signal Generators, Portable Equipment,
and NLEs.
ORDERING INFORMATION
PART NUMBER
GS1545-CQR
GS1545-CQRE3
PACKAGE
128 pin MQFP
128 pin MQFP
TEMPERATURE
0°C to 70°C
0°C to 70°C
Pb-FREE AND GREEN
No
Yes
DESCRIPTION
The GS1545 is a high performance integrated Equalizing
Receiver designed for HDTV component signals,
conforming to the SMPTE 292M standard. The GS1545
includes adjustment free adaptive cable equalization, clock
and data recovery, and serial to parallel conversion.
The Equalizer stage features DC restoration for immunity to
the DC content in pathological test patterns.
The Clock and Data Recovery stage was designed to auto-
matically recover the embedded clock signal and re-time
the data from SMPTE 292M compliant digital video signals.
There is also a selectable reclocked serial data output and
the ability to bypass the reclocker stage.
A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.
The Serial to Parallel conversion stage provides 1:20 S/P
conversion
The GS1545 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
GS1545
DDOint
SDI
SDI
EQUALIZER
CORE
DDOint ANALOG-
DIGITAL
MUX &
BUFFER
RECLOCKER
CORE
S/P CONVERTER
DATA_OUT[19:0]
PCLK_OUT
BUFFER
DDO
DDO
DDI
DDI_V
TT
DDI
(opt)
A/D
DDO_EN
SIMPLIFIED BLOCK DIAGRAM
Revision Date: June 2004
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: info@gennum.com
www.gennum.com
Document No. 522 - 28 - 05