GS4901B/GS4900B Preliminary Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
64
Name
GENLOCK
Timing
Non
Synchronous
Type
Input
Description
CONTROL SIGNAL INPUT
Signal levels are LVCMOS/LVTTL compatible.
Selects Genlock mode or Free Run mode.
When this pin is set LOW and the device has successfully genlocked the
output to the input reference, the device will enter Genlock mode. The
video clock and timing outputs will be frequency and phase locked to the
detected reference signal.
When this pin is set HIGH, the video clock and the reference-timing
generator will free-run.
By default, the GS4901B’s audio clocks will be genlocked to the output
video clock regardless of the setting of this pin.
NOTE: The user must apply a reference to the input of the device prior to
setting GENLOCK = LOW. If the GENLOCK pin is set LOW and no
reference signal is present, the generated clock and timing outputs of the
device may correspond to the internal default settings of the chip until a
reference is applied.
–
Ground Pad
–
–
Ground pad on bottom of package must be soldered to main ground
plane of PCB.
External Crystal Connection
38pF
6 X1
1M
7 X2
24pF
External Clock Source Connection
external
clock
6 X1
7 X2
NC
Notes:
1. Capacitor values listed represent the total capacitance,
including discrete capacitance and parasitic board capacitance.
2. X1 serves as an input, which may alternatively accept a 27MHz clock
source. To accomodate this, mismatched capacitor values are recommended.
Figure 1-1: XTAL1 and XTAL2 Reference Circuits
37703 - 0
April 2006
19 of 95
GENNUM [ GENNUM CORPORATION ]
